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Application of Machine Learning Techniques in Post-Silicon Debugging and Bug Localization

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Abstract

As the size of hardware (HW) design increases significantly, a huge amount of data is generated during the design simulation, emulation or prototyping. Debugging large HW designs becomes a tedious, time consuming and a bottleneck task within the function verification activities. This paper proposes the utilization of machine learning techniques to automate the diagnosis of design trace dump as well as helping in bug localization during post-silicon validation. Our framework starts by signal selection algorithm that identifies which signals to monitor during design execution. Signal selection depends on signal types as well as their connectivity network. The design is then executed and the trace dump is saved for offline analysis. Big-Data processing technique, namely, Map-Reduce is used to overcome the challenge of processing huge trace dump resulted from design running on FPGA prototype. K-means Clustering method is applied to group trace segments that are very similar and to identify the ones with a rare occurrence during the design execution. Additionally, we propose a bug localization framework in which X-means clustering is used to group the passing regression tests in clusters such that buggy tests can be detected when they fail to be assigned to any of the trained clusters. Our experimental results demonstrate the feasibility of the proposed approach in guiding the debugging effort using a group of industrial HW designs and its ability to detect multiple design injected defects using mutation-based-testing method.

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Authors and Affiliations

  1. Mentor Graphics, Siemens Business, IC Verification Solutions, Cairo, Egypt

    Eman El Mandouh

  2. Computer Engineering Department, Cairo University, Giza, Egypt

    Amr G. Wassal

Authors
  1. Eman El Mandouh
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  2. Amr G. Wassal
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Correspondence to Eman El Mandouh.

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Responsible Editor: V. D. Agrawal

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El Mandouh, E., Wassal, A.G. Application of Machine Learning Techniques in Post-Silicon Debugging and Bug Localization. J Electron Test 34, 163–181 (2018). https://doi.org/10.1007/s10836-018-5716-y

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  • DOI: https://doi.org/10.1007/s10836-018-5716-y

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