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Dynamic power-aware scheduling of real-time tasks for FPGA-based cyber physical systems against power draining hardware trojan attacks

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Abstract

The present era has witnessed deployment of reconfigurable hardware or field-programmable gate arrays (FPGAs) in diverse domains like automation and avionics, which are cyber physical in nature. Such cyber physical systems are associated with strict power budgets. Efficient real-time task-scheduling strategies exist that ensure execution of maximum number of tasks within the power budget. However, these do not consider hardware threats into account. Recent literature has exposed the existence of hardware trojan horses (HTHs). HTHs are malicious circuitry that remain dormant during testing and evade detection, but get activated at runtime to jeopardize operations. HTHs can be etched into the FPGA fabric by adversaries in the untrustworthy foundries, during fabrication of the FPGAs. Even vendors selling reconfigurable intellectual properties or bitstreams that configure the FPGA fabric for task operation may insert HTHs during writing the bitstream codes. HTHs may cause a variety of attacks which may affect the basic security primitives of the system like its integrity, confidentiality or availability. In this work, we explore how power draining ability of HTHs may reduce lifetime of the system. A self-aware approach is also proposed which detects the affected resources of the system and eradicates their use in future to facilitate system reliability. An offline–online scheduling strategy is proposed for periodic tasks which can ensure reliability of their operations till the expected lifetime of the system. Accommodating non-periodic tasks in the periodic task schedule based on available power is also focused. For experimentation, we consider tasks associated with EPFL benchmarks and demonstrate results based on the metric task success rate for periodic tasks and metric task rejection rate for non-periodic tasks.

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Abbreviations

FPGA:

Field-programmable gate array

IP:

Intellectual property

3PIP:

Third party IP vendor

HTH:

Hardware trojan horse

HDL:

Hardware description language

DPR:

Dynamic partial reconfiguration

DCM:

Dynamic clock management

PTI:

Periodic task interface

NPTI:

Non-periodic task interface

CU:

Control unit

TIA:

Task information analyzer

EDF:

Earliest deadline first

TSR:

Task success rate

TRR:

Task rejection rate

NPB:

Normalized power budget

NToA:

Normalized time of attack

NTRD:

Normalized task relative deadline

VLSI:

Very large scale integration

fn :

Total number of FPGAs

vn :

Total number of 3PIP vendors

v :

Variable which indexes the number of vendors

b :

Total number of bitstreams procured

t :

Time instant

f :

Default operational frequency

i :

Variable used for indexing tasks

\(T_{i}\) :

Task i

\(\rho _{i}\) :

Reconfiguration time of \(T_i\)

\(\epsilon _{i}\) :

Execution time of \(T_i\)

\(\alpha _{i}\) :

Arrival time of \(T_i\)

\(\delta _{i}\) :

Deadline of \(T_i\)

\(\pi _{i}\) :

Periodicity of \(T_i\)

\(\sigma\) :

Total time units in a schedule period

\(\chi\) :

Number of time units required by the control unit to operate

\(\mu\) :

Multiple factor of f

\(T_{ij}\) :

Task \(T_i\) operating on \({{FPGA}}_j\)

x :

Counting index for HTH trigger

y :

Value set by adversary for HTH trigger

sp :

Schedule period

\(P_{sp}\) :

Power dissipation in each schedule period

n :

Total number of schedule periods

q :

Number of FPGAs

p :

Order of unscheduled and available tasks at time t

\(\zeta\) :

Total number of unscheduled and available tasks at time t

\(\phi\) :

Operational frequency of an FPGA

k :

Number of schedules

S(k):

Schedule k

max(FPGA):

Maximum number of FPGAs required for execution of periodic tasks

min(FPGA):

Minimum number of FPGAs required for execution of periodic tasks

\(COUNT_{FPGA(q)}\) :

Number of malicious task executions associated with FPGA(q)

\(COUNT_{Vendor(v)}\) :

Number of malicious task executions associated with bitstreams from Vendor(v)

s :

Number of safe FPGAs

iqn :

Total number of tasks in a schedule to be executed on an FPGA

iq :

Variable which indexes tasks in a schedule to be executed on an FPGA

\(P_{reference}T_iq\) :

Reference power for executing task \(T_{iq}\)

\(P_{observed}T_iq\) :

Observed power for executing task \(T_{iq}\)

CHECK(q):

Variable for fault diagnosis

npn :

Total number of non-periodic tasks

np :

Variable for indexing non-periodic tasks

Start(AP):

Start time of available period for non-periodic task execution

End(AP):

End time of available period for non-periodic task execution

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Acknowledgements

This work is supported by the Department of Science and Technology, Government of India, INSPIRE Fellowship No. IF150916 and Intel Final Year Research Fellowship Award 2019 by Intel Corporations, India.

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  1. A. K. Choudhury School of Information Technology, University of Calcutta, Kolkata, West Bengal, India

    Krishnendu Guha, Atanu Majumder, Debasri Saha & Amlan Chakrabarti

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  1. Krishnendu Guha
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Correspondence to Krishnendu Guha.

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Guha, K., Majumder, A., Saha, D. et al. Dynamic power-aware scheduling of real-time tasks for FPGA-based cyber physical systems against power draining hardware trojan attacks. J Supercomput 76, 8972–9009 (2020). https://doi.org/10.1007/s11227-020-03184-3

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