Skip to main content
SpringerLink
Log in

A Flexible LDPC/Turbo Decoder Architecture

  • Published:
Journal of Signal Processing Systems Aims and scope Submit manuscript

Abstract

Low-density parity-check (LDPC) codes and convolutional Turbo codes are two of the most powerful error correcting codes that are widely used in modern communication systems. In a multi-mode baseband receiver, both LDPC and Turbo decoders may be required. However, the different decoding approaches for LDPC and Turbo codes usually lead to different hardware architectures. In this paper we propose a unified message passing algorithm for LDPC and Turbo codes and introduce a flexible soft-input soft-output (SISO) module to handle LDPC/Turbo decoding. We employ the trellis-based maximum a posteriori (MAP) algorithm as a bridge between LDPC and Turbo codes decoding. We view the LDPC code as a concatenation of n super-codes where each super-code has a simpler trellis structure so that the MAP algorithm can be easily applied to it. We propose a flexible functional unit (FFU) for MAP processing of LDPC and Turbo codes with a low hardware overhead (about 15% area and timing overhead). Based on the FFU, we propose an area-efficient flexible SISO decoder architecture to support LDPC/Turbo codes decoding. Multiple such SISO modules can be embedded into a parallel decoder for higher decoding throughput. As a case study, a flexible LDPC/Turbo decoder has been synthesized on a TSMC 90 nm CMOS technology with a core area of 3.2 mm2. The decoder can support IEEE 802.16e LDPC codes, IEEE 802.11n LDPC codes, and 3GPP LTE Turbo codes. Running at 500 MHz clock frequency, the decoder can sustain up to 600 Mbps LDPC decoding or 450 Mbps Turbo decoding.

This is a preview of subscription content, log in via an institution to check access.

Access this article

Log in via an institution

Price excludes VAT (USA)
Tax calculation will be finalised during checkout.

Instant access to the full article PDF.

Institutional subscriptions

Fig. 1
Fig. 2
Fig. 3
Fig. 4
Fig. 5
Fig. 6
Fig. 7
Fig. 8
Fig. 9
Fig. 10
Fig. 11
Fig. 12
Fig. 13
Fig. 14
Fig. 15
Fig. 16
Fig. 17
Fig. 18
Fig. 19
Fig. 20
Fig. 21
Fig. 22

Similar content being viewed by others

References

  1. Abbasfar, A., & Yao, K. (2003). An efficient and practical architecture for high speed turbo decoders. IEEE Vehicular Technology Conference, 1, 337–341.

    Google Scholar 

  2. Alles, M., Vogt, T., & Wehn, N. (2008). FlexiChaP: A reconfigurable ASIP for convolutional, turbo, and LDPC code decoding. In 2008 5th International symposium on turbo codes and related topics (pp. 84–89).

  3. Bahl, L., Cocke, J., Jelinek, F., & Raviv, J. (1974). Optimal decoding of linear codes for minimizing symbol error rate. IEEE Transactions on Information Theory IT-20, 284–287.

    Article  MathSciNet  MATH  Google Scholar 

  4. Berrou, C., Glavieux, A., & Thitimajshima, P. (1993). Near Shannon limit error-correcting coding and decoding: Turbo-codes. In IEEE Int. conf. commun. (pp. 1064–1070).

  5. Bickerstaff, M., Davis, L., Thomas, C., Garrett, D., & Nicol, C. (2003). A 24Mb/s radix-4 logMAP turbo decoder for 3GPP-HSDPA mobile wireless. In IEEE Int. solid-state circuit conf. (ISSCC).

  6. Blanksby, A. J., & Howland, C. J. (2002). A 690-mW 1-Gb/s 1024-b, rate-1/2 low-density parity-check code decoder. IEEE Journal of Solid-State Circuits, 37, 404–412.

    Article  Google Scholar 

  7. Bougard, B., Giulietti, A., Derudder, V., Weijers, J. W., Dupont, S., Hollevoet, L., Catthoor, F., et al. (2003). A scalable 8.7-nJ/bit 75.6-Mb/s parallel concatenated convolutional (turbo-) codec. In IEEE International solid-state circuit conference (ISSCC).

  8. Bougard, B., Giulietti, A., Van der Perre, L., & Catthoor, F. (2002). A class of power efficient VLSI architectures for high speed turbo-decoding. In IEEE conf. global telecommunications (Vol. 1, pp. 549–553).

  9. Brack, T., Alles, M., Kienle, F., & Wehn, N. (2006). A synthesizable IP core for WIMAX 802.16e LDPC code decoding. In IEEE 17th Int. symp. personal, indoor and mobile radio communications (pp. 1–5).

  10. Brack, T., Alles, M., Lehnigk-Emden, T., Kienle, F., Wehn, N., L’Insalata, N., et al. (2007). Low complexity LDPC code decoders for next generation standards. In Design, automation, and test in Europe (pp. 331–336). New York: ACM

    Google Scholar 

  11. Chen, J., Dholakia, A., Eleftheriou, E., Fossorier, M., & Hu, X. (2005). Reduced-complexity decoding of LDPC codes. IEEE Transactions on Communications, 53, 1288–1299.

    Article  Google Scholar 

  12. Dai, Y., Yan, Z., & Chen, N. (2006). High-throughput turbo-sum-product decoding of QC LDPC codes. In 40th Annual conf. on info. sciences and syst. (Vol. 11, pp. 839– 8446).

  13. Gallager, R. (1963). Low-density parity-check codes. Cambridge: MIT.

    Google Scholar 

  14. Gunnam, K. K., Choi, G. S., Yeary, M. B., & Atiquzzaman, M. (2007). VLSI architectures for layered decoding for irregular LDPC codes of WiMax. In IEEE International Conference on Communications (ICC) (pp. 4542–4547).

  15. Hagenauer, J., Offer, E., & Papke, L. (1996). Iterative decoding of binary block and convolutional codes. IEEE Transactions on Information Theory, 42(2), 429–445.

    Article  MATH  Google Scholar 

  16. Hagenauer, J., Offer, E., & Papke, L. (1996). Iterative decoding of binary block and convolutional codes. IEEE Transactions on Information Theory, 42, 429–445.

    Article  MATH  Google Scholar 

  17. He, Z., Fortier, P., & Roy, S. (2006). Highly-parallel decoding architectures for convolutional turbo codes. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 14(10), 1147–1151.

    Article  Google Scholar 

  18. Hocevar, D. (2004). A reduced complexity decoder architecture via layered decoding of LDPC codes. In IEEE workshop on signal processing systems (SIPS) (pp. 107–112).

  19. Dielissen, J., & Huisken, J. (2000). State vector reduction for initialization of sliding windows MAP. In 2nd International symposium on turbo codes and related topics.

  20. Lee, S. J., Shanbhag, N., & Singer, A. (2005). Area-efficient high-throughput MAP decoder architectures. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 13, 921–933.

    Article  Google Scholar 

  21. Lin, Y., Mahlke, S., Mudge, T., & Chakrabarti, C. (2006). Design and implementation of turbo decoders for software defined radio. In IEEE SIPS (pp. 22–27).

  22. Lu, J., & Moura, J. (2003). Turbo like decoding of LDPC codes. In IEEE Int. conf. on magnetics (pp. DT-11).

  23. MacKay, D. J. C. (1998). Turbo codes are low density parity check codes. Available online, http://www.inference.phy.cam.ac.uk/mackay/turbo-ldpc.pdf.

  24. Mansour, M. M., & Shanbhag, N. R. (2003). High-throughput LDPC decoders. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 11, 976–996.

    Article  Google Scholar 

  25. Masera, G., Piccinini, G., Roch, M., & Zamboni, M. (1999). VLSI architecture for turbo codes. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 7, 369–3797.

    Article  Google Scholar 

  26. Masera, G., Quaglio, F., & Vacca, F. (2005). Finite precision implementation of LDPC decoders. In IEEE proc. commun. (Vol. 152, pp. 1098–1102).

  27. Mohsenin, T., Truong, D., & Baas, B. (2009). Multi-split-row threshold decoding implementations for LDPC codes. In IEEE International symposium on circuits and systems (ISCAS’09) (pp. 2449–2452).

  28. Niktash, A., Parizi, H., Kamalizad, A., & Bagherzadeh, N. (2008). RECFEC: A reconfigurable FEC processor for Viterbi, turbo, Reed-Solomon and LDPC coding. In IEEE Wireless communications and networking conference (WCNC) (pp. 605–610).

  29. Oh, D., & Parhi, K. (2006). Low complexity implementations of sum-product algorithm for decoding low-density parity-check codes. In IEEE Workshop on signal processing systems (SIPS) (pp. 262–267).

  30. Prescher, G., Gemmeke, T., & Noll, T. (2005). A parametrizable low-power high-throughput turbo-decoder. In IEEE Int. conf. acoustics, speech, and signal processing (Vol. 5, pp. 25–28).

  31. Robertson, P., Villebrun, E., & Hoeher, P. (1995). A comparison of optimal and sub-optimal MAP decoding algorithm operating in the log domain. In IEEE Int. conf. commun. (ICC) (pp. 1009–1013).

  32. Rovini, M., Gentile, G., Rossi, F., & Fanucci, L. (2007). A scalable decoder architecture for IEEE 802.11n LDPC codes. In IEEE global telecommunications conference (pp. 3270–3274).

  33. Salmela, P., Sorokin, H., & Takala, J. (2008). A programmable Max-Log-MAP turbo decoder implementation. Hindawi VLSI Design, 2008, 636–640.

    Google Scholar 

  34. Scarpellino, M., Singh, A., Boutillon, E., & Masera, G. (2008). Reconfigurable architecture for LDPC and turbo decoding: A NoC case study. In IEEE 10th International symposium on spread spectrum techniques and applications (pp. 671–676).

  35. Shih, X. Y., Zhan, C. Z., Lin, C. H., & Wu, A. Y. (2008). An 8.29 mm2 52 mW multi-mode LDPC decoder design for mobile WiMAX system in 0.13 m CMOS process. IEEE Journal of Solid-State Circuits, 43, 672–683.

    Article  Google Scholar 

  36. Sun, J., & Takeshita, O. (2005). Interleavers for turbo codes using permutation polynomials over integer rings. IEEE Transactions on Information Theory, 51, 101–119.

    Article  MathSciNet  Google Scholar 

  37. Sun, Y., & Cavallaro, J. R. (2008). A low-power 1-Gbps reconfigurable LDPC decoder design for multiple 4G wireless standards. In IEEE International SOC conference (pp. 367–370).

  38. Sun, Y., & Cavallaro, J. R. (2008). Unified decoder architecture For LDPC/Turbo codes. In IEEE Workshop on Signal Processing Systems (SIPS) (pp. 13–18).

  39. Sun, Y., Karkooti, M., & Cavallaro, J. R. (2006). High throughput, parallel, scalable LDPC encoder/decoder architecture for OFDM systems. In IEEE workshop on design, applications, integration and software (pp. 39–42).

  40. Sun, Y., Karkooti, M., & Cavallaro, J. R. (2007). VLSI decoder architecture for high throughput, variable block-size and multi-rate LDPC codes. In IEEE International symposium on circuits and systems (ISCAS) (pp. 2104–2107).

  41. Sun, Y., Zhu, Y., Goel, M., & Cavallaro, J. R. (2008). Configurable and scalable high throughput turbo decoder architecture for multiple 4G wireless standards. In IEEE International conference on application-specific systems, architectures and processors (ASAP) (pp. 209–214).

  42. Thul, M. J., Gilbert, F., Vogt, T., Kreiselmaier, G., & Wehn, N. (2005). A scalable system architecture for high-throughput turbo-decoders. Journal of VLSI Signal Processing, 39, 63–77.

    Article  MATH  Google Scholar 

  43. Viterbi, A. (1998). An intuitive justification and a simplified implementation of the MAP decoder for convolutional codes. IEEE Journal on Selected Areas in Communications, 16, 260–264.

    Article  Google Scholar 

  44. Wang, Z., Chi, Z., & Parhi, K. (2002). Area-efficient high-speed decoding schemes for turbo decoders. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 10, 902–912.

    Article  Google Scholar 

  45. Wang, Z., & Cui, Z. (2007). Low-complexity high-speed decoder design for quasi-cyclic LDPC codes. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 15, 104–114.

    Article  Google Scholar 

  46. Zhang, J., & Fossorier, M. (2002). Shuffled belief propagation decoding. In Asilomar Conference on signals, systems and computers (Vol. 1, pp. 8–15).

  47. Zhang, K., Huang, X., & Wang, Z. (2009). High-throughput layered decoder implementation for quasi-cyclic LDPC codes. IEEE Journal on Selected Areas in Communications, 27(6), 985–994.

    Article  Google Scholar 

  48. Zhang, T., Wang, Z., & Parhi, K. (2001). On finite precision implementation of low density parity check codes decoder. In IEEE Int. symposium on circuits and systems (ISCAS) (Vol. 4, pp. 202–205).

  49. Zhong, H., & Zhang, T. (2005). Block-LDPC: A practical LDPC coding system design approach. IEEE Transactions on Circuits and Systems I: Fundamental Theory and Applications, 52(4), 766–775 (see also IEEE Transactions on Circuits and Systems I: Regular Papers).

    Article  MathSciNet  Google Scholar 

  50. Zhu, Y., & Chakrabarti, C. (2009). Architecture-aware LDPC code design for multiprocessor software defined radio systems. In IEEE transactions on signal processing (Vol. 57, pp. 3679–3692).

Download references

Acknowledgements

The authors would like to thank Nokia, Nokia Siemens Networks (NSN), Xilinx, Texas Instruments (TI), and US National Science Foundation (under grants CCF-0541363, CNS-0551692, CNS-0619767, CNS-0923479, and EECS-0925942) for their support of the research.

Author information

Authors and Affiliations

  1. Department of Electrical and Computer Engineering, Rice University, 6100 Main Street, Houston, TX, 77005, USA

    Yang Sun & Joseph R. Cavallaro

Authors
  1. Yang Sun
    View author publications

    You can also search for this author in PubMed Google Scholar

  2. Joseph R. Cavallaro
    View author publications

    You can also search for this author in PubMed Google Scholar

Corresponding author

Correspondence to Yang Sun.

Rights and permissions

Reprints and permissions

About this article

Cite this article

Sun, Y., Cavallaro, J.R. A Flexible LDPC/Turbo Decoder Architecture. J Sign Process Syst 64, 1–16 (2011). https://doi.org/10.1007/s11265-010-0477-6

Download citation

  • Received:

  • Revised:

  • Accepted:

  • Published:

  • Issue Date:

  • DOI: https://doi.org/10.1007/s11265-010-0477-6

Keywords

Search

Navigation