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Improving Network-on-Chip-based Turbo Decoder Architectures

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Abstract

In this work novel results concerning Network-on-Chip-based turbo decoder architectures are presented. Stemming from previous publications, this work concentrates first on improving the throughput by exploiting adaptive-bandwidth-reduction techniques. This technique shows in the best case an improvement of more than 60 Mb/s. Moreover, it is known that double-binary turbo decoders require higher area than binary ones. This characteristic has the negative effect of increasing the data width of the network nodes. Thus, the second contribution of this work is to reduce the network complexity to support double-binary codes, by exploiting bit-level and pseudo-floating-point representation of the extrinsic information. These two techniques allow for an area reduction of up to more than the 40 % with a performance degradation of about 0.2 dB.

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Notes

  1. If Log-MAP algorithms are used the result is not actually the maximum among the input values due to \(f_{c}(x)\).

  2. If we model a topology as a graph, a self-loop is an edge whose source and destination nodes coincide.

  3. Since we use three fractional bits for data representation the integer values of K we considered correspond to 0.25, 0.75, 1 and so on.

  4. The worst case corresponds to simulations where ABR is not applied

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  1. Dipartimento di Elettronica e Telecomunicazioni, Politecnico di Torino, C.so Duca degli Abruzzi 24, 10129, Torino, Italy

    Maurizio Martina & Guido Masera

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  1. Maurizio Martina
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  2. Guido Masera
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Correspondence to Maurizio Martina.

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Martina, M., Masera, G. Improving Network-on-Chip-based Turbo Decoder Architectures. J Sign Process Syst 73, 83–100 (2013). https://doi.org/10.1007/s11265-013-0733-7

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