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Low-latency histogram equalization for infrared image sequences: a hardware implementation

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Abstract

This work describes a hardware implementation of the contrast-limited adaptive histogram equalization algorithm (CLAHE). The intended application is the processing of image sequences from high-dynamic-range infrared cameras. The variant of histogram equalization implemented is the one most commonly used today. It involves dividing the image into tiles, computing a transformation function on each of them, and interpolating between them. The contrast-limiting is modified to facilitate the hardware implementation, and it is shown that the error introduced by this modification is negligible. The latency of the design is minimized by performing its successive steps simultaneously on the same frame and by exploiting the vertical blank pause between frames. The resource usage of the histogram equalization module and how it depends on its parameters has been determined by synthesis. The design has been synthesized and tested on a Xilinx FPGA. The implementation supports substituting other dynamic range reduction modules for the histogram equalization component by partial dynamic reconfiguration.

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Notes

  1. http://sipi.usc.edu/database/index.html.

  2. http://www.imagecompression.info/test_images/.

  3. The normalization factor is derived from the pixel count excluding bad pixels but including the secondary excess, which slightly biases the transformation function towards smaller pixel values. This could be corrected by deferring normalization until the transformation functions are used, when the secondary excess is known.

  4. Available from http://www.cvg.rdg.ac.uk/datasets/index.html.

  5. VHDL is one of the major hardware description languages. It stands for “VHSIC hardware description language”, where VHSIC stands for “very high speed integrated circuit”.

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Acknowledgments

The author thanks Diana Göhringer for vital tutoring in the use of the Xilinx Partial Reconfiguration design flow. Furthermore, he thanks Diana Göhringer and Thomas Perschke for proofreading the manuscript, and Lars Braun for helping overcome our FPGA board’s resistance to partial bit streams.

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Authors and Affiliations

  1. Fraunhofer Institut für Optronik, Systemtechnik und Bildauswertung, Gutleuthausstraße 1, 76275, Ettlingen, Germany

    Volker Schatz

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Appendix

Appendix

This appendix presents an overall functional description of the CLAHE implementation and shows how the components described in the main part of the paper work together. Readers intending to reproduce the design should also consult [25], where an implementation of the unmodified CLAHE algorithm is described in great detail.

Figure 11 displays a functional schematic of the operations performed while pixel values arrive at the module. Thick lines represent numerical quantities, while thin lines are boolean signals. Figure 10 defines the utilized components. As pixel values arrive, they are added to the global histogram necessary for the range determination of the preprocessing step. The windowing transformation based on the range from the previous frame is applied to the values. The range check component determines which pixel values are within the valid range. Its output prevents bad pixels from being processed by the CLAHE.

Fig. 10
figure 10

Key to the component symbols used in Figs. 11 and 12. The windowing component maps the valid input data range to the complete output data range. The range check component outputs a logical 1 if the input value is in the valid range

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Fig. 11
figure 11

Operation of the CLAHE circuit while pixel data arrive during the frame, see Fig. 5 for the tile histogram generation circuit

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In the right part of the figure, the pixel value is added to the appropriate tile histogram. This task is performed by the circuit shown in Fig. 5 the operation of which is qualified by the data valid and in-range signals. Simultaneously, it is transformed using transformation functions computed from the tile histograms of the previous frame. The transformation results are then interpolated to produce the result pixel value. See below for how the right tiles are selected.

The dotted boxes in Fig. 11 represent submodules within which other operations are performed during the inter-frame gap. These operations are shown in Fig. 12. The pixel value counters in that figure start from zero and count up to the maximum once during each vertical blank interval. The circuit on the left accumulates the global histogram and keeps updating the range registers until the corresponding boundary of the valid range has been passed. The quantities BadPixLow and BadPixHigh are the numbers of pixels at the bottom and the top of the histogram to discard as bad pixels of the camera.

Fig. 12
figure 12

Determination of the valid pixel range and generation of the tile transformation functions during the vertical blank gap. The dotted boxes represent the same submodules as in Fig. 11. A copy of the circuit on the right exists for each tile

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The submodule on the right which contains the tile histograms and transformation functions operates only on pixels which are within the range of the preprocessing step. L is the clip limit. The registers for the number of in-range pixels, the excess and the number of saturated bins are provided by the tile histogram generation circuit, see Fig. 5. The amount to be redistributed per bin is computed, it is added to the bin value, and that value is clipped again. The result is accumulated, normalized by division by the pixel count and written to the transformation LUT.

Selecting the right tiles for tile histogram generation and interpolation requires auxiliary quantities that are derived from the pixel coordinates. These are more concisely expressed as formulas than block diagrams. The horizontal tile indices are derived from the X coordinate as follows:

$$ \begin{aligned}&\hbox{HistTileX} = X / \hbox{TileWidth} \\ &\hbox{InterTileLeft} = (X - \hbox{TileWidth} / 2) / \hbox{TileWidth} \\ &\hbox{InterTileRight} = \hbox{InterTileLeft} + 1 \\ &\hbox{InterTileXFrac} = (X / \hbox{TileWidth})\;\hbox{mod}\; 1.0 - 0.5 \end{aligned} $$
(11)

HistTileX is the horizontal index of the tile histogram to which a pixel value is added. InterTileLeft and InterTileRight are the column indices of the tile transformation functions to use for interpolation. All divisions in the first two formulas are truncating integer divisions. InterTileXFrac is the fractional horizontal interpolation coefficient. Vertical tile indices and the vertical interpolation coefficient are computed analogously from the Y coordinate. Pixels in the image margins or corners have to bypass one or both of the interpolation steps, see Fig. 1 in Sect. 2.2.

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Schatz, V. Low-latency histogram equalization for infrared image sequences: a hardware implementation. J Real-Time Image Proc 8, 193–206 (2013). https://doi.org/10.1007/s11554-011-0204-y

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