Abstract
In this work, a pocket doped hetero source Silicon-on-insulator Tunneling Field Effect Transistor (SOI-TFET) with L shaped gate including back gate is proposed. The operation of this device is primarily dependent on band to band tunneling. Performance of a p-i-n TFET (proposed structure 1) is examined against the SOI double gate TFET (proposed structure 2). A brief investigation of the proposed device has been done by drain bias variation, EOT scaling, channel length modulation, pocket thickness variation, substrate dimension scaling and back gate voltage variation using Sentaurus TCAD software. The device performance is optimized for different source, drain, channel and pocket doping concentration and work function tuning of the front gate. It provides a high Ion/Ioff ratio, best reported 3.326 × 1011; steep Subthreshold Swing, SS best reported point SS 22.21 mV/decade (2 nm gate oxide) and average SS 31.74 mV/decade (3 nm gate oxide). The ON current is found to be high i.e. in the orders of mA. The proposed device is immune to short channel effects like DIBL and channel length modulation.
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Acknowledgements
This publication is an outcome of the R&D work undertaken in the project under the Visvesvaraya PhD Scheme of Ministry of Electronics & Information Technology,Government of India, being implemented by Digital India Corporation (formerly Media Lab Asia). The author give a vote of thanks to the Microelectronics Computational Laboratory, Department of Electronics and Communication Engineering, National Institute of Technology, Silchar for providing all facilities to perform our research work. We also acknowledge Prashanth Kumar, Suman Kr. Mitra, Rupam Goswami, Puja Ghosh, K Puitea and Wangkheirakpam Vandana Devi for their aid in proper handling of related software.
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Goswami, P.P., Bhowmick, B. Optimization of Electrical Parameters of Pocket Doped SOI TFET with L Shaped Gate. Silicon 12, 693–700 (2020). https://doi.org/10.1007/s12633-019-00169-7
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DOI: https://doi.org/10.1007/s12633-019-00169-7