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Simulation Study and Comparative Analysis of Some TFET Structures with a Novel Partial-Ground-Plane (PGP) Based TFET on SELBOX Structure

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Abstract

This paper proposes a novel TFET structure namely gate stacked (GS) heterojunction (HJ) partial-ground-plane (PGP) TFET with SELBOX (GSHJ-PGP-STFET) for improving the ON/OFF-state current ratio of the TFET by reducing the OFF-state current while maintaining the ON-state current nearly unaffected. Here we have done a comparative analysis of fully depleted SOI TFET and TFET on SELBOX structure with our proposed device. An extensive TCAD based simulation study has been carried out for investigating the effect of temperature on the subthreshold swing (SS), transfer characteristics, threshold voltage, and ION/IOFF ratio of the given TFET structures. The ION/IOFF ratio and SS are found to be ~1011 and 47 mV/dec respectively which is better over other two structures. Also, the proposed TFET device has improved reliability in terms of smaller effect of temperature on the performance of GSHJ-PGP-STFET as compared to the conventional SELBOX and FD-SOI TFET structures.

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Authors and Affiliations

  1. Department of Electronics Engineering, IIT (BHU), Varanasi, Uttar Pradesh, 221005, India

    Ashish Kumar Singh, Manas Ranjan Tripathy, Sweta Chander, Kamalaksha Baral, Prince Kumar Singh & S. Jit

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  1. Ashish Kumar Singh
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  2. Manas Ranjan Tripathy
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  3. Sweta Chander
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  4. Kamalaksha Baral
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  6. S. Jit
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Correspondence to Ashish Kumar Singh or S. Jit.

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Singh, A.K., Tripathy, M.R., Chander, S. et al. Simulation Study and Comparative Analysis of Some TFET Structures with a Novel Partial-Ground-Plane (PGP) Based TFET on SELBOX Structure. Silicon 12, 2345–2354 (2020). https://doi.org/10.1007/s12633-019-00330-2

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