Skip to main content
SpringerLink
Log in

InAs/Si Hetero-Junction Channel to Enhance the Performance of DG-TFET with Graphene Nanoribbon: an Analytical Model

  • Original Paper
  • Published:
Silicon Aims and scope Submit manuscript

Abstract

In this paper, a new two-dimensional analytical model for our proposed InAs/Si based double-gate dual-metal tunnel field-effect transistor (DG-TFET) with graphene nano-ribbon is presented. Incorporating group III-V material in source – channel junction, which in turn forms heterojunction results better device performance. Moreover, thin graphene nano-ribbon placed over intrinsic channel can tune the energy gap to larger extent, which supports better band-to-band (B2B) tunneling in our model. Direct tunneling model is used for Indium Arsenide (InAs), since it is direct bandgap material. Obtained Vth as 0.19 V, sub-threshold swing (SS) as 20.76 mV/decade and ION/IOFF ratio as 108 for the case of InAs/Si DG-TFET with graphene nano-ribbon shows an improvement of 48%, 36% and 10 decades respectively compared to conventional all-Si DG-TFET. Using 2-D TCAD numerical device simulator the proposed device model is designed and validated well with analytical data.

This is a preview of subscription content, log in via an institution to check access.

Access this article

Log in via an institution

Price excludes VAT (USA)
Tax calculation will be finalised during checkout.

Instant access to the full article PDF.

Institutional subscriptions

Similar content being viewed by others

References

  1. Ionescu AM, Riel H (2011) Tunnel field-effect transistors as energy-efficient electronic switches. Nature 479(7373):329–337

    Article  CAS  Google Scholar 

  2. Koswatta SO, Lundstrom MS, Nikonov DE (2009) Performance comparison between p-i-n tunneling transistors and conventional MOSFETs. IEEE Trans Electron Devices 56(3):456–465

    Article  CAS  Google Scholar 

  3. Seabaugh AC, Zhang Q (2010) Low-voltage tunnel transistors for beyond CMOS logic. Proc IEEE 98(12):2095–2110

    Article  CAS  Google Scholar 

  4. Choi WY, Park B-G, Lee JD, Liu T-JK (2007) Tunneling field-effect transistors (TFETs) with subthreshold swing (SS) less than 60 mV/dec. IEEE Electron Device Lett 28(8):743–745

    Article  CAS  Google Scholar 

  5. Thomas N, Philip Wong HS (2017) The end of Moore’s law: a new beginning for information technology. IEEE J Comput Sci Eng 19(2):41–50

    Article  Google Scholar 

  6. Dutta R, Konar SC, Paitya N (2020) Influence of gate and channel engineering on multigate tunnel FETs: a review. In: Maharatna K, Kanjilal M, Konar S, Nandi S, Das K (eds) Computational advancement in communication circuits and systems. Lecture notes in electrical engineering, vol 575. Springer

  7. Madan J, Gupta RS, Chaujar R (2017) Mathematical modeling insight of hetero gate dielectric-dual material gate-GAA-tunnel FET for VLSI/analog applications. Microsyst Technol 23(9):4091–4098

    Article  CAS  Google Scholar 

  8. Bardon MG, Neves HP, Puers R, Van Hoof C (2010) Pseudo two- dimensional model for double-gate tunnel FETs considering the junctions depletion regions. IEEE Trans Electron Devices 57(4):827–834

    Article  CAS  Google Scholar 

  9. Ilatikhameneh H, Tan Y, Novakovic B, Klimeck G, Rahman R, Appenzeller J (2015) Tunnel field-effect transistors in 2-D transition metal Dichalcogenide materials. IEEE J Explor Solid-State Comput Devices Circuits 1:12–18. https://doi.org/10.1109/JXCDC.2015.2423096

    Article  Google Scholar 

  10. Dutta R, Paitya N (2019) Electrical characteristics Assessmenton Heterojunction tunnel FET (HTFET) by optimizing various high-κ materials: HfO2/ZrO2. Int J of Innovative Technology and Exploring Engineering 8(10):393–396

    Article  Google Scholar 

  11. Verhulst AS, Soree B, Leonelli D, Vandenberghe WG, Groeseneken G (2010) Modeling the single-gate, doublegate, and gate all-around tunnel field-effect transistor. J Appl Phys 107(2):024518

    Article  Google Scholar 

  12. Choi WY, Lee W (2010) Hetero-gate-dielectric tunneling fieldeffect transistors. IEEE Trans Electron Devices 57(9):2317–2319

    Article  Google Scholar 

  13. Saurabh S, Kumar MJ (2011) Novel attributes of a dual material gate nanoscale tunnel field-effect transistor. IEEE Trans Electron Devices 58(2):404–410

    Article  CAS  Google Scholar 

  14. Pourfath M, Kosina H, Selberherr S (2007) Tunneling CNTFETs. J Comput Electron 6(1):243–246

    Article  Google Scholar 

  15. Goharrizi AY, Pourfath M, Fathipour M, Kosina H (2012) Device performance of graphene nanoribbon field-effect transistors in the presence of line-edge roughness. IEEE Trans Electron Devices 59(12):3527–3532

    Article  Google Scholar 

  16. Zhao P, Feenstra RM, Gu G, Jena D (2013) SymFET: a proposed symmetric graphene tunneling field-effect transistor. IEEE Trans Electron Devices 60(3):951–957

    Article  Google Scholar 

  17. Hwang WS, Zhao P, Kim SG et al (2019) Room-temperature graphene-nanoribbon tunneling field-effect transistors. npj 2D Mater Appl 3:43

    Article  Google Scholar 

  18. Jain P, Prabhat V, Ghosh B (2015) Dual metal-double gate tunnel field effect transistor with mono/hetero dielectric gate material. J Comput Electron 14(2):537–542

    Article  CAS  Google Scholar 

  19. Cappy A et al (1980) Comparative Potential Performance of Si, GaAs, GaInAs, InAs Submicrometer-Gate FET’s. IEEE Trans. on Electron Devices ED-27(11)

  20. Young KK (1989) Short-channel effect in fully depleted SOI MOSFETs. IEEE Trans Electron Devices 36(2):399–402

    Article  Google Scholar 

  21. Dutta R, Paitya N (2019) TCAD performance analysis of P-I-N tunneling FETS under surrounded gate structure. SSRN-Elsevier

  22. TCAD Atlas Manual, Silvaco, Inc., CA 95054, USA, 2015

Download references

Acknowledgements

This work was supported in part by All India Council for Technical Education (AICTE), Govt. of India under Research Promotion Scheme for North-East Region (RPS-NER) vide ref.: File No. 8-139/RIFD/RPS-NER/Policy-1/2018-19.

Special acknowledgement also goes to Dr. Nitai Paitya for facilitating the authors with Nanoelectronics Lab, Sikkim Manipal Institute of Technology (SMIT)- Sikkim, India, for this research work.

Author information

Authors and Affiliations

  1. Department of Electronics and Communication Engineering, Surendra Institute of Engineering & Management, Siliguri, West Bengal, 734009, India

    Ritam Dutta

  2. Department of Electronics and Communication Engineering, Sikkim Manipal Institute of Technology, Rangpo, Sikkim, 737136, India

    Ritam Dutta & Nitai Paitya

  3. Department of Electrical and Electronics Engineering, Mangalam College of Engineering, Ettumanoor, Kerala, 686631, India

    T. D. Subash

Authors
  1. Ritam Dutta
    View author publications

    You can also search for this author in PubMed Google Scholar

  2. T. D. Subash
    View author publications

    You can also search for this author in PubMed Google Scholar

  3. Nitai Paitya
    View author publications

    You can also search for this author in PubMed Google Scholar

Corresponding author

Correspondence to Ritam Dutta.

Additional information

Publisher’s Note

Springer Nature remains neutral with regard to jurisdictional claims in published maps and institutional affiliations.

Rights and permissions

Reprints and permissions

About this article

Check for updates. Verify currency and authenticity via CrossMark

Cite this article

Dutta, R., Subash, T.D. & Paitya, N. InAs/Si Hetero-Junction Channel to Enhance the Performance of DG-TFET with Graphene Nanoribbon: an Analytical Model. Silicon 13, 1453–1459 (2021). https://doi.org/10.1007/s12633-020-00546-7

Download citation

  • Received:

  • Accepted:

  • Published:

  • Issue Date:

  • DOI: https://doi.org/10.1007/s12633-020-00546-7

Keywords

Search

Navigation