Design and Analysis of Low Power and High Frequency Current Starved Sleep Voltage Controlled Oscillator for Phase Locked Loop Application

Abstract

This paper presents a current starved sleep voltage-controlled oscillator(VCO) for the Phase Locked Loop (PLL) at high frequency with low power. The PLL’s significance is still vital in many communication systems today, such as GPS system, clock data recovery, satellite communication, and frequency synthesizer. The PLL design for low voltage applications has many challenges, such as leakage power, supply voltage fluctuations. The VCO is an electronic oscillator which produces oscillating frequency for the control voltage. Current starved VCO is popular among the oscillators because it offers the right balance between low area, wide tuning range. VCO’s power consumption is most significant and has an impact on the performance of the low power PLL. This work proposes the many inverter delay techniques (stack delay cell, sleepy stack delay cell, sleep delay cell) techniques in current starved VCO, resulting in reduced leakage power consumption. Introducing the sleep transistor between the pull-up MOSFET and supply voltage in an inverter induces a reverse bias, causing the reduction in sub-threshold leakage current when both are in off condition. The current starved sleep VCO has been designed using CMOS 90nm technology and investigated at the operating frequency of 1 GHz and wide tuning range from 0.5GHz-5.8GHz. It is to be observed that the power dissipation of the VCO is 8.12μ W, which is 2.3X lesser to the conventional VCO, the phase noise of -115dBc/Hz @1MHz and figure of merit value of -228.2dBc/Hz.