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Gate Oxide Variability Analysis of a Novel 3 nm Truncated Fin–FinFET for High Circuitry Performance

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Abstract

In this work, we examined the analog and circuitry amplifying capacity of our novel 3 nm Truncated Fin Junctionless bulk FinFET (n-type) with two different oxide thicknesses at this small scale of gate length. Both oxide widths of high K-material HfO2 have their own individual benefits, due to high gate controllability as compared to conventional FinFETs having SiO2 as a gate oxide. The device works best with Tox = 1 nm in terms of power amplification. When tested with this width of gate oxide, we end up with increase of 59.18%, 7.22% and 12.11 times at corresponding peak values of Unilateral power gain (Gu), IP3 and fmax. This actually evident the enhanced performance of TF-FinFET for A.C applications at this high range of frequency of the input signal. When device tested at Tox = 1 nm, we end up with the increase of 45%, 21.45%, 16% and decrease of 65% at the corresponding peak values of Intrinsic delay (ti), Transconductance (gm), Drain current (ID) and OFF-state current (IOFF). These results of simulation also showed the compatibility of TF-FinFET in terms of high-performance analog application. After these analyses, we can expect a strong potential for wide variety of applications to high-speed System on chip from this device.

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Acknowledgments

The authors are grateful to Microelectronics Research Lab, Department of Applied Physics, Delhi Technological University for supporting this research work.

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  1. Applied Physics Department, Delhi Technological University, New Delhi, India

    Mridul Prakash Kashyap & Rishu Chaujar

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  1. Mridul Prakash Kashyap
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  2. Rishu Chaujar
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Correspondence to Rishu Chaujar.

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Kashyap, M.P., Chaujar, R. Gate Oxide Variability Analysis of a Novel 3 nm Truncated Fin–FinFET for High Circuitry Performance. Silicon 13, 3249–3256 (2021). https://doi.org/10.1007/s12633-020-00734-5

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  • DOI: https://doi.org/10.1007/s12633-020-00734-5

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