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Drain Current Modelling of Asymmetric Junctionless Dual Material Double Gate MOSFET with High K Gate Stack for Analog and RF Performance

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Abstract

This paper presents the continuous 2D analytical modelling of electrostatic potential, threshold voltage (Vth), subthreshold swing, drain induced barrier lowering (DIBL) and drain current of asymmetric junctionless dual material double gate MOSFET with high K gate stack (AJDMDG Stack MOSFET). The electrostatic potential is achieved by solving Poisson’s equation with the help of the parabolic approximation method. Analytical results are verified by using ATLAS TCAD Device simulator. A comparative study of short channel effects (SCEs) of AJDMDG Stack MOSFET and asymmetric junctionless dual material double gate MOSFET with high K gate stack (SJDMDG Stack MOSFET) has been observed in order to show the efficacy of asymmetry condition such as gate oxide asymmetry, gate work function asymmetry etc. for suppressing SCEs. Further, analog/RF performance parameters such as transconductance (gm), output resistance (rout), intrinsic gain, transconductance generation factor (TGF), cut-off frequency (fT), maximum frequency (fmax), gain bandwidth product (GBW) etc. of AJDMDG Stack MOSFET are observed and compared the results with SJDMDG Stack MOSFET structure. Results reveal that AJDMDG Stack MOSFET has better efficacy for RF applications.

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References

  1. International technology roadmap for semiconductors 2009 Edition and 2010 Update. http://www.itrs.net. Accessed 2018

  2. Björkqvist K, Arnborg T (1981) Short Channel effects in MOS-transistors. Phys Scr 24:418–421

    Google Scholar 

  3. Taur JY, Buchanan DA, Chen W, Frank DJ, Ismail KE, Lo SH et al (1997) CMOS scaling into the nanometer regime. Proc IEEE 85:486–504

    Google Scholar 

  4. Mohsenifar S, Shahrokhabadi MH (2015) Gate stack high-κ materials for Si-based MOSFETs past, present, and futures. Microelectronics and Solid State Electronics 4(1):12–24

    Google Scholar 

  5. Datta S (2013) Recent advances in high performance CMOS transistors: from planar to non-planar. Electrochem Soc Interfac 22(1):41–46. https://doi.org/10.1149/2.F04131if

    Article  CAS  Google Scholar 

  6. Colinge JP (2004) Multiple-Gate SOI MOSFETs. Solid State Electron 48(6):897–905

    CAS  Google Scholar 

  7. Xie Q, Wang Z, Taur Y (2017) Analysis of short-channel effects in JUNCTIONLESS DG MOSFETs. IEEE Transactions on Electron Devices 64:3511–3514

    CAS  Google Scholar 

  8. Gnudi A, Reggiani S, Gnani E, Baccarani G (2013) Semianalytical model of the subthreshold current in short-channel junctionless symmetric double-gate field-effect transistors. IEEE Trans Electron Devices 60:1342–1348

    Google Scholar 

  9. Colinge JP, Lee CW, Afzalian A, Dehdashti Akhavan N, Yan R, Ferain I, Razavi P, O'Neill B, Blake A, White M, Kelleher AM, McCarthy B, Murphy R (2010) Nanowire transistors without junctions. Nat Nanotechnol 5(3):225–229

    CAS  PubMed  Google Scholar 

  10. Bari S, De D, Sarkar A (2015) Effect of gate engineering in JLSRG MOSFET to suppress SCEs: an analytical study. Physica E: Low-dimensional Systems and Nanostructures 67:143–151

    CAS  Google Scholar 

  11. Biswal SM, Baral B, De D, Sarkar A (2015) Analytical subthreshold modeling of dual material gate engineered nano-scale junctionless surrounding gate MOSFET considering ECPE. Superlattice Microst 82:103–112

    CAS  Google Scholar 

  12. Venkateshwar Reddy G, Jagadesh Kumar M (2005) A new dualmaterial double-gate (DMDG) nanoscale SOI MOSFET-twodimensional analytical modeling and simulation. IEEE Trans Nanotechnol 4(2):260–268

    Google Scholar 

  13. Singh J, Gadi V, Kumar MJ (2016) Modeling a dual-material-gate Junctionless FET under full and partial depletion conditions using finite-differentiation method. IEEE Transactions on Electron Devices 63(6):2282–2287

    CAS  Google Scholar 

  14. Chiang TK (2012) A quasi-two-dimensional threshold voltage model for short-channel junctionless double-gate MOSFETs. IEEE Trans. Electron Devices 59(9):2284–2289

    Google Scholar 

  15. Sarkar A, De S, Dey A, Sarkar CK (2012) 1/f noise and analogue performance study of short-channel cylindrical surrounding gate MOSFET using a new subthreshold analytical pseudo-two-dimensional model. IET circuits, devices & systems 6(1):28–34

    Google Scholar 

  16. Sarkar A, De S, Sarkar CK (2012) Asymmetric halo and symmetric SHDMG & DHDMGn-MOSFETs characteristic parameter modeling. IJNM, Wiley, USA 26(1):41–55

    Google Scholar 

  17. Chakraborty A, Sarkar A (2017) Analytical modeling and sensitivity analysis of dielectric-modulated junctionless gate stack surrounding gate MOSFET (JLGSSRG) for application as biosensor. J Comput Electron 16(3):556–567

    CAS  Google Scholar 

  18. Baral B, Das AK, De D, Sarkar A (2015) An analytical model of triple-material double-gate metal–oxide–semiconductor field-effect transistor to suppress short-channel effects. Electronic Networks, Devices and Fields, International Journal of Numerical Modelling

    Google Scholar 

  19. Wang P, Zhuang Y, Li C, Liu Y, Jiang Z (2015) Potential-based threshold voltage and subthreshold swing models for junctionless double-gate metal-oxide-semiconductor field-effect transistor with dual-material gate. Int J Numer Model Electron Networks Devices Fields 29(2):230–242. https://doi.org/10.1002/jnm.2067

    Article  Google Scholar 

  20. Darwin S, Arun Samuel TS (2020) A holistic approach on Junctionless dual material double gate (DMDG) MOSFET with high k gate stack for low power digital applications. Silicon 12:393–403

    CAS  Google Scholar 

  21. Ghosh P, Haldar S,Gupta RS, GuptaM (2012) Analytical modeling and simulation for dual metal gate stack architecture (DMGSA) cylindrical /surrounded gate MOSFET. J Semicond Technol Sci 12(4):458–466 https://doi.org/10.5573/JSTS.2012.12.4.458

  22. Adak S, Swain SK, Dutta A, Rahaman H, Sarkar CK (2016) Influence of channel length and high-K oxide thickness on subthreshold DC performance of graded channel and gate stack DGMOSFETs. NANO: Brief Reports and Reviews 11(9):1650101-1–1650101-6. https://doi.org/10.1142/S1793292016501010

    Article  CAS  Google Scholar 

  23. Kumari V, Modi N, Saxena M, Gupta M (2015) Theoretical investigation of dual material Junctionless double gate transistor for analog and digital performance. IEEE Transactions on Electron Devices 62(7):2098–2105

    Google Scholar 

  24. Biswas K, Sarkar A, Sarkar CK (2015) Impact of barrier thickness on analog, RF and linearity performance of nanoscale DG heterostructure MOSFET. Superlattice Microst 86:95–104

    CAS  Google Scholar 

  25. Sarkar A, Sarkar CK (2013) RF and analogue performance investigation of DG tunnel FET. International Journal of Electronics Letters 1(4):210–217

    CAS  Google Scholar 

  26. Biswas K, Sarkar A, Sarkar CK (2018) Fin shape influence on analog and RF performance of junctionless accumulation-mode bulk FinFETs. Microsyst Technol 24(5):2317–2324

    CAS  Google Scholar 

  27. Sarkar A (2014) Study of RF performance of surrounding gate MOSFET with gate overlap and underlap. Adv Nat Sci Nanosci Nanotechnol 5(3):035006

    CAS  Google Scholar 

  28. Sarkar A, De S, Dey A, Sarkar CK (2011) A new analytical subthreshold model of SRG MOSFET with analogue performance investigation. Int J Electron 99(2):267–283

    Google Scholar 

  29. Basak A, Chanda M, Sarkar A (2019) Drain current modelling of unipolar junction dual material double-gate MOSFET (UJDMDG) for SoC applications. Microsyst Technol

  30. Koley K, Syamal B, Kundu A, Mohankumar N, Sarkar CK (2012) Subthreshold analog/RF performance of underlap DG FETs with asymmetric source/drain extensions. Microelectron Reliab 52(11):2572–2578

    Google Scholar 

  31. Koley K, Dutta A, Saymal B, Saha SK, Sarkar CK (2013) Subthreshold analog/RF performance enhancement of underlap DG FETs with high-K spacer for low power applications. IEEE Transaction on Electron Devices 60(1):63–69

    Google Scholar 

  32. Gupta A, Maurya N, Rai S (2017) Impact of dielectric pocket on analog/RF performance of short channel double gate MOSFET, 2017 4th international conference on power, Control & Embedded Systems (ICPCES), Allahabad: 1-6

  33. Chebaki E, Djeffal F, Hichem F, Bentrcia T (2016) Improved analog/RF performance of double gate junctionless MOSFET using both gate material engineering and drain/source extensions. Superlattice Microst 92:80–91

    CAS  Google Scholar 

  34. Sharma RK, Bucher M (2012) Device design engineering for optimum analog/RF performance of Nanoscale DG MOSFETs. IEEE Trans Nanotechnol 11(5):992–998

    Google Scholar 

  35. Mohankumar N, Syamal B, Sarkar CK (2010) Influence of channel and gate engineering on the analog and RF performance of DG MOSFETs. IEEE Transactions on Electron Devices 57(4):820–826

    CAS  Google Scholar 

  36. Roy NC, Gupta A, Rai S (2015) Analytical surface potential modeling and simulation of junctionless double gate (JLDG) MOSFET for ultra-low-power analog/RF circuits. Microelectron J 46(10):916–922

    CAS  Google Scholar 

  37. Ghosh D, Parihar MS, Armstrong GA, Kranti A (2012) High-performance Junctionless MOSFETs for ultralow-power analog/RF applications. IEEE Electron Device Letters 33(10):1477–1479

    CAS  Google Scholar 

  38. Swain SK, Dutta A, Adak S, Pati SK, Sarkar CK (2016) Influence of channel length and high-K oxide thickness on subthreshold analog/RF performance of graded channel and gate stack DGMOSFETs. Microelectron Reliab 61:24–29

    CAS  Google Scholar 

  39. Narendar V, Girdhardas KA (2018) Surface potential modeling of Graded-Channel gate-stack (GCGS) high-K dielectric dual-material double-gate (DMDG) MOSFET and analog/RF performance study. Silicon 10:2865–2875

    CAS  Google Scholar 

  40. Young KK (1989) Short-channel effects in fully depleted SOI MOSFET's. IEEE Transaction on Electron Device 36(2):399–402

    Google Scholar 

  41. Jin X, Liu X, Kwon HI, Lee JH, Lee JH (2013) A subthreshold current model for nanoscale short channel junctionless MOSFETs applicable to symmetric and asymmetric double-gate structure. Solid State Electron 82:77–81

    CAS  Google Scholar 

  42. Suzuki K, Sugii T (1995) Analytical models for n+−p+ double gate SOI MOSFET’s. IEEE Trans Electron Devices 42(11):1940–1948

    CAS  Google Scholar 

  43. Arora ND, Rios R, Huang CL, Raol K (1994) PCIM: a physically based continuous short-channel IGFET model for circuit simulation. IEEE Trans Electron Devices 41(6):988–997

    Google Scholar 

  44. Roldan JB, Gamiz F, Lopez-Villanueva JA, Carceller JE (1997) Modeling effects of electron velocity overshoot in a MOSFET. IEEE Trans Electron Devices 44(5):841–846

    Google Scholar 

  45. Roldan JB, Gamiz F, Lopez-Villanueva JA, Cartujo P, Carceller JE (1998) A model for the drain current of deep submicrometer MOSFET’s including electron-velocity overshoot. IEEE Trans Electron Devices 45(10):2249–2251

    Google Scholar 

  46. Reddy GV, Kumar MJ (2005) A new dual material double gate (DMDG) nanoscale SOI MOSFET: Two dimensional analytical modelling and simulation. IEEE Trans Electron Devices 4(2):260–268

    Google Scholar 

  47. Chen YG, Kuo JB, Yu Z, Dutton RW (1995) An analytical drain current model for short-channel fully-depleted ultrathin siliconon- in-sulatornMOS devices. Solid State Electron 38(12):2051–2057

    CAS  Google Scholar 

  48. Sakurai T, Newton AR (1990) Alpha-power law MOSFET model and its applications to CMOS inverter delay and other formulas. IEEE J Solid State Circuits 25(2):584–594

    Google Scholar 

  49. Bhattacharyya AB (2009) Compact MOSFET models for VLSI design. Wiley, New York

    Google Scholar 

  50. ATLAS Device Simulation Software, Santa Clara, CA, USA, 2015

  51. Ward DE, Dutton RW (1978) A charge-oriented model for MOS transistor capacitances. IEEE J Solid State Circuits 13(5):703–708

    Google Scholar 

  52. Chakraborty A, Sarkar A (2015) Investigation of analog/RF performance of staggered heterojunctions based nanowire tunnelling field-effect transistors. Superlattice Microst 80:125–135

    CAS  Google Scholar 

  53. Biswal SM, Baral B, De D, Sarkar A (2016) Study of effect of gate-length downscaling on the analog/RF performance and linearity investigation of InAs-based nanowire tunnel FET. Superlattice Microst 91:319–330

    CAS  Google Scholar 

  54. Basak A, Sarkar A (2020) Quantum analytical model for lateral dual gate UTBB SOI MOSFET for analog/RF performance. Silicon

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Authors and Affiliations

  1. Department of ECE, Brainware University, Kolkata, West Bengal, India

    Arighna Basak

  2. Department of ECE, Kalyani Government Engineering College, Kalyani, India

    Angsuman Sarkar

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  1. Arighna Basak
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  2. Angsuman Sarkar
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Correspondence to Arighna Basak.

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Basak, A., Sarkar, A. Drain Current Modelling of Asymmetric Junctionless Dual Material Double Gate MOSFET with High K Gate Stack for Analog and RF Performance. Silicon 14, 75–86 (2022). https://doi.org/10.1007/s12633-020-00783-w

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  • DOI: https://doi.org/10.1007/s12633-020-00783-w

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