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Parametric Investigation and Design of Junctionless Nanowire Tunnel Field Effect Transistor

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Abstract

An integrated design based on Gate-All-Around (GAA) silicon Junctionless (JL) vertical profile Nanowire (NW) structure has been proposed for JL-NW-Tunnel-Field Effect Transistor (JL-NW-TFET). A uniform high doping concentration (10−19) has been used to make the device a Junctionless structure. The parametric variations of the JL-NW-TFET have been analyzed such as ON-current (ION), OFF-current (IOFF), ON-OFF ratio of current (ION/OFF) and Subthreshold-Slope (SS). Therefore, work function of gate metal (4.4 eV to 4.8 eV), thickness of oxide (1.0 nm to 2.0 nm), diameter of Nanowire (10 nm to 30 nm) and channel length (22 nm to 65 nm) has been varied by implementing device structure in SILVACO Atlas Tools. The optimum parameters of the device have been observed as: maximum ION (3.73 × 10−6 A/μm), minimum IOFF (2.97 × 10−20 A/μm), Low SS (19.40 mV/dec) and high ION/OFF (3.35 × 1013). It has been proposed that these optimum parameter characteristics are immune to short channel effects and preferred for low power applications in nano regime.

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Data used for the results are available in the manuscript.

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Acknowledgements

We thank the Group, department of Electronics and Communication Engineering, NIT Jalandhar and VLSI Design Group NITTTR Chandigarh for their interest in this work and useful comments to draft the final form of the paper. The support of SERB, Government of India, Project (EEQ/2018/000444) is gratefully acknowledged. We would like to thank NIT Jalandhar and NITTTR Chandigarh for lab facilities and research environment to carry out this work.

Funding Statement

The authors declare that they have no funding available for the publication chargers of open access. We have received financial support from Science and Engineering Research Board, Government of India for computation and simulation tools to carry out the proposed work.

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Authors and Affiliations

  1. Nanoelectronics Research Lab, Dr. B.R. Ambedkar National Institute of Technology, Jalandhar, India

    Parveen Kumar

  2. National Institute of Technical Teachers Training and Research, Chandigarh, India

    Balwinder Raj

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  1. Parveen Kumar
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  2. Balwinder Raj
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We has been proposed Junctionless Nanowire Tunnel-Field Effect Transistor (JL-NW-TFET), which are immune to short channel effects and preferred for low power applications in nano regime.

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Correspondence to Parveen Kumar.

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Kumar, P., Raj, B. Parametric Investigation and Design of Junctionless Nanowire Tunnel Field Effect Transistor. Silicon 14, 6031–6037 (2022). https://doi.org/10.1007/s12633-021-01371-2

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