Abstract
In nanoscale FETs, the confined geometry and increased packaging density induce increased power density, which translates into larger heat generation. The substrate’s low thermal conductivity also leads to poor heat dissipation, leading to a further rise in temperature and aggravated self-heating effects (SHEs). The incessant scaling of transistor size demands a rigorous study on the impact of SHEs and ambient temperature variations on advanced MOSFET structures’ electrical characteristics. Therefore, in this work, an investigation on the electro-thermal (ET) behaviour of the nanoscale RingFET has been conducted using the Sentaurus TCAD device simulator. The hydrodynamic carrier transport model has been used in 3-D ET simulations to analyze the ET behaviour of the RingFET. A comparative analysis of the DC characteristics with and without SHEs has been presented via current-voltage and transconductance-voltage characteristics, which are further used to compute the ZTC (zero temperature coefficient) bias point. A detailed analysis of the device’s electrical behaviour with the variation in channel length, gate oxide thickness, substrate doping, and drain radius has also been presented. Finally, the influence of SHEs on device characteristics at various ambient temperatures has also been reported.
Similar content being viewed by others
Data Availability
Not applicable.
References
Moore GE (1965) Cramming more components onto integrated circuits. Electron Magz 38:114–117
Datta S (2016) Transistor innovation in the 21st century — A lesson in serendipity, in 74th Annual Device Research Conference (DRC), Newark, DE, USA, 19-22
Jin L (2007) What makes Moore’s law continue? — Recent advances in semiconductor, in 7th International Conference on ASIC, Guilin, China, 12
Saramekala GK (2017) Modeling and simulation of subthreshold characteristics of short-channel fully-depleted recessed-source/Drain SOI MOSFETs. http://ethesis.nitrkl.ac.in/8642/
Zheng P, Connelly D, Ding F, King Liu TJ (2015) FinFET evolution toward stacked-nanowire FET for CMOS technology scaling. IEEE Trans Electron Dev 62:3945–3950
Song J, Yu B, Yuan Y, Taur Y (2009) A review on compact modeling of multiple-gate MOSFETs. IEEE Trans Circuits Syst I 56:1858–1869
Colinge JP (2004) Multiple-gate SOI MOSFETs. Solid-State Electron 48:897–905
Song J, Yu B, Xiong W, Hsu CH, Cleavelin CR, Ma M et al (2007) Experimental hardware calibrated compact models for 50 nm n-channel FinFETs. In: Proc IEEE Conf SOI, 131-132
Dessai G, Dey A, Gildenblat G, Smit GDJ (2009) Symmetric linearization method for double-gate and surrounding-gate MOSFET model. Solid-State Electron 53:548–556
Padovese JA, Yojo LS, Rangel RC, Sasaki KRA, Martino JA (2018) Back Enhanced SOI MOSFET as UV Light Sensor, in 33rd Symposium on Microelectronics Technology and Devices (SBMicro), Bento Gonçalves, Brazil, 1-3
Pejović MM, Pejović MM, Jaksic AB, Stankovic KD, Markovic SA (2012) Successive gamma-ray irradiation and corresponding post-irradiation annealing of pMOS dosimeters. Nucl Technol Radiat 27:341–345
Ehringfeld C, Schmid S, Poljanc K, Kirisits C, Aiginger H, Georg D (2005) Application of commercial MOSFET detectors for in vivo dosimetry in the therapeutic X-ray range from 80 kV to 250 kV. Phys Med Biol 50:289–303
Lee CW, Ishabele F et al (2010) Performance estimation of junctionless multigate transistors. Solid-State Electron 54:97–103
Sallese JM, Jazaeri F, Barbut L, Chevillon N, Lallement C (2013) A common core model for junctionless nanowires and symmetric double-gate FETs. IEEE Trans 60:4277–4280
Verhulst AS, Vandenberghe WG, Maex K, Groeseneken G (2017) Tunnel field-effect transistor without gate-drain overlap. Appl Phys Lett 91(3):053102
Zhang Y, Krishnamoorthy S, Johnson JM, et al (2015) Interband tunneling for hole injection in III-nitride ultraviolet emitters. Appl Phys Lett 106(3):141103
Lima AD (1996) Effective aspect-ratio and gate-capacitance in circular geometry MOS transistors. Solid-State Electron 39:1524–1525
Williams N, Silva H, Gokirmak A (2012) Nanoscale RingFETs. IEEE Electron Device Lett 33:1339–1341
Lima JAD, Gimenez SP (2009) A novel overlapping circular-gate transistor and its application to power MOSFETs. ECS Trans 23:361–369
Kumar S, Kumari V, Saxena M, Gupta M (2013) Hot carrier reliability and linearity performance investigation of nanoscale RingFET for RFIC design. In: 9th International Conference on Microwaves, Antenna Propagation and Remote Sensing, 40-44
Kumar S, Kumari V, Singh S, Saxena M, Gupta M (2015) Nanoscale-RingFET: an analytical sub-threshold drain current model including SCE’s. IEEE Trans Electron Dev 62:3965–3972
Singh K, Kumar S, Tiwari PK, Yadav AB, Dubey S, Jit S (2019) Semianalytical threshold voltage model of a double-gate nanoscale RingFET for terahertz applications in radiation-hardened (Rad-Hard) environments. J Elec Mater 48:6366–6371
Kumar S, Kumari V, Singh S, Saxena M, Gupta M (2018) Sub-threshold drain current model of double gate RingFET (DG-RingFET) architecture: an analog and linearity performance investigation for RFIC design. IETE Tech Rev 35(2):169-179
Kumar A, Srinivas PSTN, Tiwari PK (2019) An insight into self-heating effects and its implications on hot carrier degradation for silicon-nanotube-based Double Gate-All-Around (DGAA) MOSFETs. IEEE J Electron Dev 7:1100–1108
Kumar MJ, Orouji AA (2006) Investigation of a new modified source/drain for diminished self-heating effects in nanoscale MOSFETs using computer simulation. Phys E Low-Dimensional Syst Nanostruct 33:134–138
Wang L, Brown AR, Nedjalkov M et al (2014) 3D coupled electro-thermal FinFET simulations including the fin shape dependence of the thermal conductivity. In: Proc. Int. Conf. Simul. Semicond. Process. Devices (SISPAD), 269–272
Yoo SW, Kim H, Kang M, Shin H (2016) Analysis on self-heating effect in 7 nm node bulk finfet device. J Semicond Technol Sci 16:204–209
Venkateswarlu S, Sudarsanan A, Singh SG, Nayak K (2018) Ambient temperature-induced device self-heating effects on Multi-Fin Si n-FinFET Performance. IEEE Trans Electron Dev 65:2721–2728
Sentaurus Device User Guide (2016) Version N-2017.09, Synopsys, Mountain View, CA, USA
Sjoblom G, Westlinder J, Olsson J (2005) Investigation of the thermal stability of reactively sputter-deposited TiN MOS gate electrodes. IEEE Trans Electron Dev 52:2349–2352
Osman AA, Osman MA (1998) Investigation of high temperature effects on MOSFET gate transconductance. In: 4th International High Temperature Electronics Conference Proceedings, 301-304
Kang SM, Leblebici Y (1995) CMOS digital integrated circuits analysis and design. McGraw-Hill Education, New York
Goel AK, Tan TH (2006) High-temperature and self-heating effects in fully depleted SOI MOSFETs. Microelectron J 37:963–975
Acknowledgements
The work is carried out in the Device Simulation Laboratory of IIT Patna. There is no external funding to support the work. Sahil Singh and PSTN Srinivas contributed to the manuscript equally.
Author information
Authors and Affiliations
Contributions
The idea is formulated by Dr. P. K.Tiwari and Arun Kumar. Sahil Singh and PSTN Srinivas peformed the necessary simualtions using TACD and provided the data for the results and dicussion. The paper is drafted by Sahil Singh, PSTN Srinivas and Aun kumar, and edited by Dr. P. K.Tiwari.
Corresponding author
Ethics declarations
Ethics Approval and Consent to Participate
Not applicable.
Consent for Publication
Not applicable.
Conflict of Interest
The authors declare that they have no conflict of interest.
Additional information
Publisher’s Note
Springer Nature remains neutral with regard to jurisdictional claims in published maps and institutional affiliations.
Rights and permissions
About this article
Cite this article
Singh, S., Srinivas, P.S.T.N., Kumar, A. et al. Physical Insight into Self-heating Induced Performance Degradation in RingFET. Silicon 14, 7585–7593 (2022). https://doi.org/10.1007/s12633-021-01491-9
Received:
Accepted:
Published:
Issue Date:
DOI: https://doi.org/10.1007/s12633-021-01491-9