Abstract
VLSI is an enduring technology which is used to change the entire digital element into autonomy, some real-time opportunities are characterized under Very Large Scale Integration such as low power application, testing, MOS technology etc. This research focused on signal processing in low power VLSI design, in existing system the backend IC fabrication process illustrates system-level design by using digital logic elecment. An existing digital element consist of different functions of adders such as carry select, ripple carry adder, carry skip adder, carry look ahead adder, which has consume more area, delay, and power. To improve the efficiency of digital design a novel majority carry save adder is proposed and incorporate with a structured tree multiplier, this research produce an optimized carry save adder design in digital filter for improve the signal to noise ratio. The proposed innovative carry save adder is constructed by using majority logic and implemented into a digital FIR filter, this new technique consumes low power, delay-free carry circuit and less number of gate counts. The proposed adder has achieved 96 % efficiency in terms of gate count, delay, and power compared with existing analysis. Digital system design produces 83.5 % efficiencyin an existing system and it required the maximum number of gate count and an increasing number of delays when compared with recent research. The design summary is analyzed by using XILINX 14.7 ISE synthesis and the implementation process is highly reached with the help of MATLAB 2018a. The proposed design is implemented into Biomedical Application for reducing noise and improving signal to noise ratio.
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Aathilakshmi, S., Vimala, R. & Britto, K.R.A. An elegance of novel digital filter using majority logic on pipelined architecture for SNR improvement in signal processing. J Ambient Intell Human Comput (2021). https://doi.org/10.1007/s12652-021-03197-7
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DOI: https://doi.org/10.1007/s12652-021-03197-7