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Design and Implementation of CNTFET-Based Reversible Combinational Digital Circuits Using the GDI Technique for Ultra-low Power Applications

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Abstract

It is obvious that the design of low power digital circuits is very important. Hence, reversible logic can be used as the great method for reducing power consumption. In this paper, we attempt to present various CNTFET-based reversible combinational circuits such as multiplexers and decoders by simultaneous use of the reversible Fredkin gate and Gate Diffusion Input (GDI) technique. At first, we illustrate the block diagram of multiplexers and decoders according to the definition of reversible gates. Then, we introduce the design approach of CNTFET-based circuits by using the GDI technique. All structures are simulated using Synopsys HSPICE with standard 32 nm CNTFET technology in various conditions including temperature 27 °C, simulation time from zero to 100 ns, and other parameters are the variable. In this work, we investigate the variation effect of supply voltage, temperature, number of nanotubes, and chiral vector in performance evaluation of the mentioned circuits. In addition, the ECPOT analysis is reported. According to the results, the proposed CNTFET-based reversible multiplexers achieve a significant saving in average power consumption (approximately 99.99% for 2:1 multiplexer, 99.95% for 4:1 multiplexer, 99.96% for 8:1 multiplexer compared with the best previous work) and the average power consumption for 16:1 multiplexer is 25.47 nw. The proposed CNTFET-based reversible decoders have high performance in the average power consumption (approximately 99.99% for 2:4 decoder, 99.99% for 3:8 decoder, and 99.22% for 4:16 decoder compared with the best previous work). Moreover, applying these suggested circuits significantly improves the speed, PDP, and EDP of complex arithmetic structures.

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References

  1. Moore, G. E. (1998). Cramming more components onto integrated circuits. Proceedings of the IEEE, 86(1), 82–85.

    Article  Google Scholar 

  2. Roy, K., Mukhopadhyay, S., & Mahmoodi-Meimand, H. (2003). Leakage current mechanisms and leakage reduction techniques in deep-submicrometer CMOS circuits. Proceedings of the IEEE, 91(2), 305–327.

    Article  Google Scholar 

  3. Liang, J., et al. (2014). Design and evaluation of multiple valued logic gates using pseudo N-type carbon nanotube FETs. IEEE Transactions on Nanotechnology, 13(4), 695–708.

    Article  Google Scholar 

  4. Thapliyal, H., & Ranganathan, N. (2010). Design of reversible sequential circuits optimizing quantum cost, delay, and garbage outputs. ACM Journal on Emerging Technologies in Computing Systems, 6(4), 14.

    Article  Google Scholar 

  5. Landauer, R. (1961). Irreversibility and heat generation in the computing process. IBM Journal of Research and Development, 5(3), 183–191.

    Article  MathSciNet  Google Scholar 

  6. Bennett, C. H. (1973). Logical reversibility of computation. IBM Journal of Research and Development, 17(6), 525–532.

    Article  MathSciNet  Google Scholar 

  7. Singh, P., et al. (2015). Reducing delay and quantum cost in the novel design of reversible memory elements. Procedia Computer Science, 57, 189–198.

    Article  Google Scholar 

  8. Thakral, S., & Bansal, D. (2016). Fault tolerant ALU using parity preserving reversible logic gates. International Journal of Modern Education and Computer Science, 8(8), 51.

    Article  Google Scholar 

  9. Mamun, M., Al, S., Menville, D. (2014). Quantum cost optimization for reversible sequential circuit. arXiv preprint arXiv:1407.7098.

  10. Haghparast, M., & Monfared, A. T. (2018). Designing novel quaternary quantum reversible subtractor circuits. International Journal of Theoretical Physics, 57(1), 226–237.

    Article  MathSciNet  Google Scholar 

  11. Khan, M. H. (2014). Design of reversible synchronous sequential circuits using pseudo Reed-Muller expressions. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 22(11), 2278–2286.

    Article  Google Scholar 

  12. Panahi, A., et al. (2016). CNFET-based approximate ternary adders for energy-efficient image processing applications. Microprocessors and Microsystems, 47, 454–465.

    Article  Google Scholar 

  13. Mastoori, M. S., & Razaghian, F. (2016). A novel energy-efficient ternary successor and predecessor using CNTFET. Circuits, Systems, and Signal Processing, 35(3), 875–895.

    Article  Google Scholar 

  14. Moaiyeri, M. H., et al. (2013). A universal method for designing low-power carbon nanotube FET-based multiple-valued logic circuits. IET Computers and Digital Techniques, 7(4), 167–181.

    Article  Google Scholar 

  15. Maleknejad, M. et al. (2018). A low-power high-speed hybrid multi-threshold full adder design in CNFET technology. J Comput Electron, p. 1-11.

  16. Srinivasu, B., & Sridharan, K. (2016). Low-complexity multiternary digit multiplier design in CNTFET technology. IEEE Transactions on Circuits and Systems II: Express Briefs, 63(8), 753–757.

    Article  Google Scholar 

  17. Tabrizchi, S., Azimi, N., & Navi, K. (2017). A novel ternary half adder and multiplier based on carbon nanotube field effect transistors. Frontiers of Information Technology & Electronic Engineering, 18(3), 423–433.

    Article  Google Scholar 

  18. Nagapavani, T., Rajmohan, V., Rajendaran, P. (2011). Optimized shift register design using reversible logic. in Electronics Computer Technology (ICECT), 2011 3rd International Conference on. IEEE.

  19. Haghparast, M., & Shams, M. (2012). Optimized nanometric fault tolerant reversible bcd adder. Research Journal of Applied Sciences, Engineering and Technology, 4(9), 1067–1072.

    Google Scholar 

  20. Joshi, P., Sahu, I.(2017). A review paper on design of an asynchronous counter using novel reversible SG gate. in Innovative Mechanisms for Industry Applications (ICIMIA), 2017 International Conference on. IEEE.

  21. Abir, M. A. I. et al. (2016). Design of parity preserving reversible sequential circuits. in Informatics, Electronics and Vision (ICIEV), 2016 5th International Conference on. IEEE.

  22. Lin, S., Kim, Y.-B., & Lombardi, F. (2011). CNTFET-based design of ternary logic gates and arithmetic circuits. IEEE Transactions on Nanotechnology, 10(2), 217–225.

    Article  Google Scholar 

  23. Eatemadi, A., et al. (2014). Carbon nanotubes: properties, synthesis, purification, and medical applications. Nanoscale Research Letters, 9(1), 393.

    Article  Google Scholar 

  24. Moaiyeri, M. H., Doostaregan, A., & Navi, K. (2011). Design of energy-efficient and robust ternary circuits for nanotechnology. IET Circuits, Devices and Systems, 5(4), 285–296.

    Article  Google Scholar 

  25. Kim, Y. B., Kim, Y.-B., Lombardi, F.. (2009). A novel design methodology to optimize the speed and power of the CNTFET circuits. in Circuits and Systems, 2009. MWSCAS'09. 52nd IEEE International Midwest Symposium on. IEEE.

  26. Appenzeller, J. (2008). Carbon nanotubes for high-performance electronics—progress and prospect. Proceedings of the IEEE, 96(2), 201–211.

    Article  Google Scholar 

  27. Morgenshtein, A., Moreinis, M., & Ginosar, R. (2004). Asynchronous gate-diffusion-input (GDI) circuits. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 12(8), 847–856.

    Article  Google Scholar 

  28. Foroutan, V., et al. (2014). Design of two Low-Power full adder cells using GDI structure and hybrid CMOS logic style. Integration, the VLSI Journal, 47(1), 48–61.

    Article  Google Scholar 

  29. Shukla, V., et al. (2013). Novel design of a 4: 1 multiplexer circuit using reversible logic. International Journal of Computational Engineering Research, 3(10), 0.

    Google Scholar 

  30. Hv, R. A., Chinmaye, R., Muralidhara, K. (2012). Design, optimization and synthesis of efficient reversible logic binary decoder. International Journal of Computers and Applications, 46(6)

  31. Majumdar, R., Saini, S. (2015). A novel design of reversible 2: 4 decoder. in Signal Processing and Communication (ICSC), 2015 International Conference on. IEEE.

  32. Anugraha, R. V., Durga, D. S., Avudaiammam, R. (2017). Design and performance analysis of 2: 1 multiplexer using multiple logic families at 180 nm technology. in Recent Trends in Electronics, Information & Communication Technology (RTEICT), 2017 2nd IEEE International Conference on. IEEE.

  33. Singh, P., Chandel, R. (2017). Design and performance analysis of digital circuits using carbon nanotube transistors. in Inventive Communication and Computational Technologies (ICICCT), 2017 International Conference on. IEEE.

  34. Adarsh, C. S. D., Lakshmi, T. V., and Kamaraju, M. (2017). Implementation and comparative analysis of double gate low power multiplexers using dynamic logic styles. in Electronics, Communication and Aerospace Technology (ICECA), 2017 International conference of. IEEE.

  35. Pannu, N., Prakash, N. R. (2016). A power-efficient multiplexer using reversible logic. Indian Journal of Science and Technology, 9(30).

  36. Khan, A. et al. (2016). Low-power PTL-based multiplexer design in±0.9 V 32nm dual-gate Si FinFET. in Devices, Circuits and Systems (ICDCS), 2016 3rd International Conference on. IEEE

  37. Balobas, D., & Konofaos, N. (2017). Design of low-power high-performance 2–4 and 4–16 mixed-logic line decoders. IEEE Transactions on Circuits and Systems II: Express Briefs, 64(2), 176–180.

    Article  Google Scholar 

  38. Sonam, A. A novel design of reversible 2: 4 & 3: 8 decoder

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Correspondence to Maryam Shaveisi.

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Shaveisi, M., Rezaei, A. Design and Implementation of CNTFET-Based Reversible Combinational Digital Circuits Using the GDI Technique for Ultra-low Power Applications. BioNanoSci. 10, 1063–1083 (2020). https://doi.org/10.1007/s12668-020-00777-3

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