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Design for Stuck-at Fault Testability in Toffoli–Fredkin Reversible Circuits

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Abstract

An intense trade-off arises between testing, hardware and speed of electronic circuits. An efficient design for testability methodology for the detection of stuck-at faults in reversible circuits is presented in this paper by exploiting the properties of Toffoli and Fredkin gates. An (\(n+1\)) dimensional general test set depicted in the paper is found complete for the detection of single and multiple stuck-at faults in the modified circuit. A set of benchmark circuits are taken for experimentation where the proposed work achieved a reduction up to \(25.0\%\) in gate cost and \(35.8\%\) in quantum cost when compared to the existing work of the area that proves its efficacy towards the reduction in hardware cost with limited degradation in speed.

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Acknowledgements

The authors are thankful to National Academy of Sciences, India, for providing platform for the researchers. Sincerest thanks to the editor, his team and reviewers for providing faster response and insightful comments in the way of improvement of the work. This work is done at the Department of ECE, NIT Kurukshetra and Department of ECE, ABES Institute of Technology Ghaziabad. There is no research Grant involved during the completion of this work with the authors of this manuscript.

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Correspondence to Hari Mohan Gaur.

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Gaur, H.M., Singh, A.K. & Ghanekar, U. Design for Stuck-at Fault Testability in Toffoli–Fredkin Reversible Circuits. Natl. Acad. Sci. Lett. 44, 215–220 (2021). https://doi.org/10.1007/s40009-020-00967-3

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  • DOI: https://doi.org/10.1007/s40009-020-00967-3

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