Abstract
An intense trade-off arises between testing, hardware and speed of electronic circuits. An efficient design for testability methodology for the detection of stuck-at faults in reversible circuits is presented in this paper by exploiting the properties of Toffoli and Fredkin gates. An (\(n+1\)) dimensional general test set depicted in the paper is found complete for the detection of single and multiple stuck-at faults in the modified circuit. A set of benchmark circuits are taken for experimentation where the proposed work achieved a reduction up to \(25.0\%\) in gate cost and \(35.8\%\) in quantum cost when compared to the existing work of the area that proves its efficacy towards the reduction in hardware cost with limited degradation in speed.
References
Bennett CH (1973) Logical reversibility of computation. IBM J Res Dev 17(6):525–532
Nielsen M, Chuang IL (2000) Quantum computation and quantum information. Cambridge University Press, Cambridge
iNEMI-Roadmap Executive Summary Highlights (2019) International electronics manufacturing initiative. https://www.inemi.org/
Gaur HM, Singh AK, Ghanekar U (2018) Testing of reversible logic circuits: an analysis. Integr VLSI J 62:50–67
Gaur HM, Singh AK, Ghanekar U (2015) A review on online testability for reversible logic. Proc Comput Sci 70:384–391
Gaur HM, Singh AK, Ghanekar U (2018) In-depth comparative analysis of reversible gates for designing logic circuits. Proc Comput Sci 125:810–817
Chakraborty A (2005) Synthesis of reversible logic circuits with universal test set and C-testability of reversible iterative logic arrays. In: Proceedings of 18th IEEE international conference on VLSI design. pp 249–254
Ibrahim M, Chowdhury AR, Hafiz M, Babu, HMH (2008) Minimization of CTS of k-CNOT circuits for SSF and MSF model. In: International symposium on defect and fault tolerance of VLSI systems, pp 290–298
Rahman H, Kole DK, Das DK, Bhattacharya BB (2011) Fault diagnosis in reversible circuits under missing-gate fault model. Int J Comput Electr Eng 37:475–485
Hays JP, Polian I, Becker B (2004) Testing of missing-gate faults in reversible circuits. In: Proceedings of Asian test symposium, pp 100–105
Gaur HM, Singh AK, Ghanekar U (2018) Testable design of reversible circuits using parity preserving gates. IEEE Des Test 35(4):56–64
Wille R, Große D, Teuber L, Dueck GW, Drechsler R (2008) RevLib: an online resource for reversible functions and reversible circuits. In: International symposium on multi-valued logic. http://www.revlib.org/cite.php
Chandra J, De D (2017) Nanocommunication network design using QCA reversible crossbar switch. Nano Commun Netw 13:20–33
Chandra J, De D (2017) Circuit switching with quantum-dot cellular automata. Nano Commun Netw 14:16–28
Acknowledgements
The authors are thankful to National Academy of Sciences, India, for providing platform for the researchers. Sincerest thanks to the editor, his team and reviewers for providing faster response and insightful comments in the way of improvement of the work. This work is done at the Department of ECE, NIT Kurukshetra and Department of ECE, ABES Institute of Technology Ghaziabad. There is no research Grant involved during the completion of this work with the authors of this manuscript.
Author information
Authors and Affiliations
Corresponding author
Additional information
Publisher's Note
Springer Nature remains neutral with regard to jurisdictional claims in published maps and institutional affiliations.
Rights and permissions
About this article
Cite this article
Gaur, H.M., Singh, A.K. & Ghanekar, U. Design for Stuck-at Fault Testability in Toffoli–Fredkin Reversible Circuits. Natl. Acad. Sci. Lett. 44, 215–220 (2021). https://doi.org/10.1007/s40009-020-00967-3
Received:
Revised:
Accepted:
Published:
Issue Date:
DOI: https://doi.org/10.1007/s40009-020-00967-3