Skip to main content
SpringerLink
Log in

Analysis and minimization of crosstalk noise in copper interconnects for high-speed VLSI circuits

  • S.I. : Visvesvaraya
  • Published:
CSI Transactions on ICT Aims and scope Submit manuscript

Abstract

Due to the rapid advances of technologies, the scaling of parameters are decreasing. In VLSI (Very Large Scale Integration) technology, the feature size of integrated circuits (IC) has driving reduced in terms of power, speed, area and cost characteristics. The decreasing the sizes in sub-quarter microns, spacing between the components on-chip VLSI design and the signal switching time in terms of pico seconds or even less. As a result, the signal integrity (SI) issues are occurring at higher frequencies and high data rates. The evaluation of crosstalk noise between the coupled interconnect is one of the prominent issue in designing of high-speed ICs. In this paper, investigated the crosstalk noise of coupled copper (Cu) interconnect models with analytically at 32 nm technology nodes. Also, investigated the crosstalk reduction with shield insertion technique and increasing physical spacing between the coupled lines. For the low power VLSI applications, the shield insertion technique is preferable for reducing the crosstalk effects in coupled interconnects.

This is a preview of subscription content, log in via an institution to check access.

Access this article

Log in via an institution

Price excludes VAT (USA)
Tax calculation will be finalised during checkout.

Instant access to the full article PDF.

Institutional subscriptions

Fig. 1
Fig. 2
Fig. 3
Fig. 4
Fig. 5
Fig. 6

Similar content being viewed by others

References

  1. Zhang XJ, Jiang W, Gao L, li H (2016) Impact of cross talk on signal integrity of high speed density ceramic package for IC. In: IEEE international conference on electronic packaging technology

  2. Paul CR (2006) Introduction to electromagnetic compatibility. Wiley, New York, 1992, (2nd ed)

  3. Paul CR (2008) Analysis of multiconductor transmission lines. Wiley, Hoboken, 1994, (2nd ed)

  4. Catt I (1967) Crosstalk (noise) in digital systems. IEEE Trans Electron Comput 16(6):743–763

    Article  Google Scholar 

  5. Vittal A, Sadowska M (1997) Crosstalk reduction for VLSI. IEEE Trans Comput-Aided Des Integr Circuits Syst 16(3):290–298

    Article  Google Scholar 

  6. Zhang J, Friedman EG (2006) Crosstalk modeling for coupled RLC interconnects with application to shield insertion. IEEE Trans Very Large Scale Integr (VLSI) Circuits 14(6):641–646

    Article  Google Scholar 

  7. Wu TL, Buesink F, Canavero F (2013) Overview of signal integrity and EMC design technologies on PCB: fundamentals and latest progress. IEEE Trans Electromagn Compat 55(4):624–638

    Article  Google Scholar 

  8. Nakhla M, Achar R (2001) Simulation of high-speed interconnects. Proc IEEE 89(5):693–728

    Article  MATH  Google Scholar 

  9. Bogatin E Signal and power integrity-simplified, Second edition, Prentice Hall Modern Semiconductor Design Series

  10. Ullah MS, Chowdhury MH (2017) Analytical models of high-speed RLC interconnect delay for complex and real poles. IEEE Trans Very Large Scale Integr (VLSI) Syst 25(6):1831–1841

    Article  Google Scholar 

  11. Hall SH, Heck HL (2009) Advanced signal integrity for high-speed digital designs. Wiley, Hoboken

    Book  Google Scholar 

  12. Hedari P, Abbaspour S, Pedram M Interconnect energy in high speed ULSI circuits. Dept of EE and CS, University of California, Irvine, CA 92697

  13. Yuan CP, Trick TN (1982) A simple formula for the estimation of the capacitance of two-dimensional interconnects in VLSI circuits. IEEE Electron Device Lett 3:391–393

    Article  Google Scholar 

  14. Delorme N, Belleville M, Chilo J (1996) Inductance and capacitance analytic formulas for VLSI interconnection. Electron Lett 32:996–997

    Article  Google Scholar 

  15. Hall SH, Hall GW, McCall JA (2000) High-speed digital system design. Wiley, Hoboken

    Google Scholar 

  16. Kose S, Salman E, Friedman EG (2011) Shielding methodologies in the presence of power/ground noise. IEEE Trans VLSI Syst 19(8):1458–1468

    Article  Google Scholar 

  17. Wong SC, Lee GY, Ma D-J (2000) Modeling of interconnect capacitance, delay, and crosstalk in VLSI. IEEE Trans Semicond Manuf 13(1):108–111

    Article  Google Scholar 

  18. Zhang J, Friedman EG (2006) Crosstalk modeling for coupled RLC interconnects with application to shield insertion. IEEE Trans Very Large Scale Integr Syst 14(6):641–646

    Article  Google Scholar 

  19. Zhang J, Friedman EG (2004) Effect of shield insertion on reducing crosstalk noise between coupled interconnects. 2004 IEEE international symposium on circuits and systems (IEEE Cat. No.04CH37512), vol 2, pp II-529–32

  20. Zhang J, Friedman EG (2004) Mutual inductance modeling for multiple RLC interconnects with application to shield insertion. IEEE International SOC Conference proceedings

  21. Ghoneima M, Ismail YI, Khellah MM, Tschanz JW, De V (2006) Formal derivation of optimal active shielding for. Comput Des 25(5):821–836

    Google Scholar 

  22. Kaul H, Sylvester D, Blaauw D (2002) Active shielding of RLC global interconnects, Proceedings of the 8th ACM/IEEE International Workshop on Timing Issues in the Specification and Synthesis of Digital Systems - TAU

Download references

Acknowledgements

This research has been sponsored by YFRF, Visvesvaraya Ph.D. scheme (MeitY), GOI. The Research grants file number is PhD-MLA-4(63)/2015-16. Authors would like to thank the Principal, University College of Engineering, Osmania University for support.

Author information

Authors and Affiliations

  1. Electronics and Communication Engineering Department, University College of Engineering, Osmania University, Hyderabad, India

    Rajendra Naik Bhukya & Raju Mudavath

Authors
  1. Rajendra Naik Bhukya
    View author publications

    You can also search for this author in PubMed Google Scholar

  2. Raju Mudavath
    View author publications

    You can also search for this author in PubMed Google Scholar

Corresponding authors

Correspondence to Rajendra Naik Bhukya or Raju Mudavath.

Rights and permissions

Reprints and permissions

About this article

Check for updates. Verify currency and authenticity via CrossMark

Cite this article

Bhukya, R.N., Mudavath, R. Analysis and minimization of crosstalk noise in copper interconnects for high-speed VLSI circuits. CSIT 7, 81–86 (2019). https://doi.org/10.1007/s40012-019-00243-w

Download citation

  • Received:

  • Accepted:

  • Published:

  • Issue Date:

  • DOI: https://doi.org/10.1007/s40012-019-00243-w

Keywords

Search

Navigation