Research work report on design, control and implementation of next generation power electronic converters for HVDC applications

Abstract

This report covers the research work being carried out under the Visvesvaraya PhD Scheme for Electronics & IT.

Appendix

• Achieved Technical results and the Expected Results to be Achieved in the next 1-year and 3-years horizons:

The technical results achieved so far are listed below in a point by point manner.

• a. MMC implementation

A 15-kW 3-phase 7-level MMC prototype has been developed in laboratory at IIT Bombay. This setup is being considered as the benchmark topology prototype for evaluating the new converter topologies and control resulting from the research works carried out under YFRF scheme. This prototype has been tested for various different operating and control conditions, namely, pre-charging of submodule capacitors, standalone mode of operation of MMC and grid-connected four-quadrant modes of operation of MMC.

• b. Improvement of power handling capability of MMC using circulating current control

One of the goal of this project is to enhance the power handling capability of HVDC converter. A circulating current control scheme has been proposed for MMC, which reduces the peak value of current carried by the MMC switches for the same power output. Hence, this scheme enables the MMC to utilize lower current rated semiconductor switches or enhance its power handling capability with the same rated switches.

• c. DC fault tolerant operation of MMC

The MMC with half-bridge SMs cannot block the fault current during the DC side fault in HVDC. Hence, due to this large current during fault, the system may get damaged. To block the DC side fault current at-least 50% of SMs in each arm should be replaced with full-bridge SMs. In the developed laboratory MMC prototype, 3 SMs are replaced with full-bridge SMs to test the performance of the MMC during DC side fault. Initially the system is started in its normal mode and after sometime, a fault is created in DC side. The controller detected the fault and blocks the pulses to the switches. Hence, the current is seized and the converter is protected.

• d. Thyristor-IGBT based hybrid submodule for MMC

As discussed earlier, one of the goals of this project is to use hybrid converter structure for HVDC by combining IGBTs and thyristors. In line with this, a new submodule proposed for MMC, which makes converter dc fault tolerant and has lower conduction losses, which results in higher efficiency.

• e. DC fault tolerant hybrid multilevel converter topologies for HVDC applications

One of the main limitations of the conventional MMC-HVDC system is its inability to block dc fault current. To tackle this problem, different techniques and topologies have been discussed in literature. This work focuses on comparative evaluation of the existing dc fault tolerant topologies on the basis of required number of switches and capacitors.

• f. Parallel hybrid converter: derived topologies and control

Parallel hybrid converter (PHC) is the most promising topology for high power applications due to its series connected chain-links on dc side and smaller submodule capacitors. Moreover, in PHC, the chain-link SMs are not in the main conduction path and the H-bridges are switched at fundamental frequency, which leads to lower semiconductor losses. However, the dc and ac side of the PHC are strongly coupled which lead to a fixed output voltage without using a dedicated control to tackle this issue. Moreover, PHC loses controls during dc fault. Various methods have been proposed in literature to decouple the dc and ac side of the converter and to make it tolerant to dc fault. In this work, a review of these state of art control strategies is presented. This work contributes in summarizing key benefits and limitations of various existing control methods through extensive analyses and simulation studies.

• g. Series-stacked hybrid modular converter with dc fault blocking capability

The three-phase series modular multilevel converter (SMMC) is an interesting option HVDC systems and also for tapping power from HVDC lines. This work proposes a series-stacked hybrid MMC, which uses both unipolar as well as bipolar SMs for attaining dc fault blocking capability. The bipolar SMs are used to limit or block the fault current by injecting negative capacitor voltages. The number of FBSMs required in the proposed topology is only one-third of the total number of SMs in the three-phase converter. On the other hand, in the conventional MMC, at-least half of the SMs should be FBSMs for dc fault blocking. Hence the proposed topology offers significant reduction in size, cost and loss. Three different circuit configurations are proposed on the basis of the proposed topology. This work also presents capacitance size calculation of the SMs used in the proposed topology so that its voltage deviation remains within a predefined maximum limit.

• h. A New H-Bridge Hybrid Modular Converter (HBHMC) for HVDC Application

An H-bridge hybrid modular converter (HBHMC) is proposed for high-voltage direct current (HVDC) applications in this workFor a three-phase system, three HBHMCs are connected either in series (series-HBHMC) or in parallel (parallel-HBHMC) across the dc-link. A detailed comparison between HBHMC and other hybrid topologies is performed on the basis of required number of switches and capacitors. The HBHMC has the features of dc fault blocking capability, lower footprint structure, and extra degree of freedom for submodules capacitor voltage balancing. The efficacy of the HBHMC-based HVDC system for three-phase balanced and unbalanced grid conditions and its fault-tolerant capability are validated using PSCAD simulation studies. Furthermore, the feasibility of the proposed converter under normal and dc fault conditions and of the proposed capacitor voltage control scheme is validated experimentally by using a three-phase grid-connected HBHMC laboratory prototype.

The technical results that are expected in the next 1 year are listed in the following:

• a. Sensor-less suppression control of MMC

Conventionally, the arm currents in MMC are sensed and the circulating current (CC) is suppressed using one of current controller such as PR controller in stationary reference frame, PI controllers in rotating frame and many others. In the proposed method, which we are working on at present, the arm currents are not sensed. Instead the capacitor voltage of each inserted SM is used to suppress the CC. It enhances the reliability and reduces the system cost, complexity in control and sensitivity on control parameters.

• b. DC Fault Tolerant Modified Parallel Hybrid Converter with Enhanced Operating Range

It is discussed earlier that the parallel hybrid converter is a promising topology for HVDC systems. However, it suffers from some limitation, which limits its widespread use. We are working on a modified parallel hybrid converter (MPHC) for HVDC applications with wide operating range and dc-fault tolerant capabilities. A novel control technique is proposed for capacitors voltage balancing of MPHC. The capacitor size design methodology, loss calculation of the converter and self-excited pre-charging mechanism are also being investigated.

• c. Modular directed series multilevel converter for HVDC applications

A novel modular directed series multilevel converter (MDSMC) is proposed in this work, which offers more compact structure and higher efficiency. The proposed topology requires smallest capacitor size. The working of MDSMC is verified by developing various component level models in PSCAD/EMTDC. The ability of the converter to provide wide range of modulation index (MI) variation is also being verified.

• d. Improved Balancing and Sensing of Submodule Capacitor Voltages in MMC

Capacitor voltage balancing is necessary in Modular Multilevel Converters. Voltage controlled oscillator is used for capacitor voltage measurement in reported literature where voltage sensor is required to be calibrated. In the work that is undergoing at present, a voltage sensing method that does not need calibration of individual voltage sensors is used for capacitor voltage measurement. Open loop phase shifted carrier pulse width modulation (PSCPWM) method is used and sorting algorithm is employed for capacitor voltage balance. A method of sorting capacitor voltages that selects the modules to be inserted directly based on logic equations is used as compared to the conventional methods of arranging them in ascending or descending order. This facilitates use of Field Programmable Gate Array for sorting.

• e. Circulating Current Optimization Control of MMC

This ongoing work proposes a circulating current optimization control (CCOC) scheme for MMC, which reduces the arm current peak value without increasing the SMs capacitors size for the same maximum voltage ripples. It enables the MMC to handle more power with the same rated switches. This controller works on the principle of controlling the magnitude and phase angle of CC to follow their respective optimized references.

The technical results that are expected in the next 3 years are listed in the following:

• a. During the next 3 years, the most optimal converter topologies and control will be proposed, which will offer significant improvements in power handling capability of the HVDC converters. As described before, this will be achieved by devising suitable submodule/converter configurations with both voltage as well as current sharing ability. The control flexibility, operating range, performance in fault and transient conditions of this new configuration are also expected to be superior to the existing ones.

• b. Another important technical results that are expected to be achieved in the next 3 years are corresponding to the combined features of VSC and CSC in a single HVDC converter. These converters will have wider operating range, control flexibility, operating range, and improved performance in fault and transient conditions compared to the existing CSC based HVDC classic.

• c. In the next 3 years, the of using SiC devices in HVDC converters will be extensively explored. The expected outputs will be in terms of compact converter structure, smaller passive components, higher reliability and higher power handling capability of HVDC converters. Another expected output from this project is also a compact, reliable and modular converter structure for high power applications using SiC devices.

• List of Major Publications and Patents Obtained due to YFRF Support

Journal papers:

• [1] M. Ghat and A. Shukla, “A New H-Bridge Hybrid Modular Converter (HBHMC) for HVDC Application: Operating Modes, Control, and Voltage Balancing”, IEEE Trans. Power Electronics, no. 8, vol. 33, pp. 6537–6554, Aug. 2018.

Patents:

• [1] A. Shukla, Y. A. Rudrasimha and M. Ghat, “Sub-Module for a Modular Multi-Level Converter (MMC),” Indian Patent 201821014637, 2018.

• [2] A. Reddy and A. Shukla, “Modular multilevel converter including switch matrix”, Indian Patent 201821005628, 2018.

• [3] A. Reddy and A. Shukla, “Circulating current controller (CCC) controlling arm current in modular multilevel converter and a method thereof”, Indian Patent 201821021181, 2018.

Conference papers:

• [1] M. B. Ghat and A. Shukla, “Series-Stacked Hybrid Modular Converter with DC Fault Blocking Capability for HVDC Application”, in Proc. IEEE ECCE, pp. 5536–5543, Sept. 2018.

• [2] S. D. Joshi, M. C. Chandorkar and A. Shukla, “Improved balancing and sensing of submodule capacitor voltages in modular multilevel converters”, in Proc. IEEE ECCE, pp. 670–677, Sept. 2018.

• [3] S. K. Patro and A. Shukla, “Modular directed series multilevel converter for hvdc applications”, in Proc. IEEE ECCE, pp. 5552–5558, Sept. 2018.

• [4] S. K. Patro and A. Shukla, “DC fault tolerant modified parallel hybrid converter with enhanced operating range”, in Proc. IEEE ECCE, pp. 119–126, Sept. 2018.

• [5] M. B. Ghat, A. Reddy and A. Shukla, “DC fault tolerant hybrid multilevel converter topologies for high power applications”, in Proc. IEEE PEDES, pp. 1–6, Dec. 2018.

• [6] Y. A. Rudrasimha, M. B. Ghat and A. Shukla, “A new hybrid submodule for MMC with dc fault ride-through capability”, in Proc. IEEE PEDES, pp. 1–6, Dec. 2018.

• [7] S. K. Patro and A. Shukla, “Parallel hybrid converter: derived topologies and control”, in Proc. IEEE PEDES, pp. 1–6, Dec. 2018.

• [8] I. C. Rath, A. Kadam and A. Shukla, “A novel three-phase transformerless inverter with negative grounding for pv application”, in Proc. IEEE PEDES, pp. 1–6, Dec. 2018.

• The way in which the Fellowship Facilitated this Work?

This fellowship has been a great support in facilitating this research work. Two PhD students supported under this scheme are working on the relevant areas under my supervision at IIT Bombay. These two are very good students and they have delivered excellent results in quick time. Because of the research grant provided under this scheme, rapid experimental verification of the proposed principles and topologies have been possible. This is further helping in publishing the obtained results in major IEEE journals and conferences. On the top of it, the research fellowship provided under this scheme has helped in building extra motivation and confidence in doing good research work. All these combined together and also because of the flexible nature of research grant provided, the research is leading towards a creative and innovative path, which is also reflecting in many patent applications resulting from this research work.