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PUF: a new era in IoT security

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Abstract

Physically unclonable function (PUF) is one of the most advocated security primitives which extracts the uncontrollable intrinsic physical property of the fabrication process to generate secret bits for authentication, random number generation and key generation. Ring oscillator (RO) PUF is the widely adopted PUF design to implement in FPGA platform, but it is highly error prone to environmental noise (i.e. temperature and voltage). The configurable RO (CRO) PUF is advocated to resolve this issue without increasing the area overhead. This paper proposes an enhanced CRO framework which uses latch instead of inverter to build an RO. The use of dedicated latch (i.e. available in an FPGA) in place of inverter eliminates the restriction to use odd number of delay units (inverters) in an RO configuration. The proposed design efficiently utilizes the resources found in a configurable logic block to increase the number of RO configurations while using the same area. Also, it provides the flexibility to include a latch in an RO configuration which in turns improve the reliability and the security as well. Experimental results on Xilinx Spartan 3E FPGA establish that the proposed design exhibits high stability despite varying environmental conditions without using any error correcting code or post-processing technique.

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Acknowledgements

The research grant provided by the YFR fellowship greatly helped to boost my research work. I have developed two laboratory essential for my research work, (i) Hardware security Laboratory. (ii) Assistive Technology Laboratory (Under process). Also, I have attended and presented a research paper in 26th IFIP/IEEE International Conference on Very Large Scale Integration (VLSI-SoC 2018), 8–10 October, Verona, Italy and Two research scholars supervised by me attended the 32nd IEEE International System-on-Chip Conference (SOCC 2019), 3–6 September, 2019, Singapore under the aegis of contingency grant of YFRF.

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  1. Computer Science and Engineering Department, National Institute of Technology Durgapur, Durgapur, India

    Bibhash Sen

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  1. Bibhash Sen
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Correspondence to Bibhash Sen.

Additional information

Area of research work: Hardware Security, Physical Unclonable Function (PUF) for Field Programmable Gate Arrays (FPGA), Hardware Trojan, Assistive Technology.

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Sen, B. PUF: a new era in IoT security. CSIT 8, 185–191 (2020). https://doi.org/10.1007/s40012-020-00293-5

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  • DOI: https://doi.org/10.1007/s40012-020-00293-5

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