Abstract
This paper reviews the need of a high performance wireline communication in the background of wirelessly connected billions of sensor nodes by 2020s. It compares the performance of the state-of-the-art wireline transceivers and underlines the challenges in improving the performance in the midst of tapering in CMOS technology scaling. This paper elaborates on the ongoing research to track the increasing bandwidth requirements in processing platforms with an affordable power budget. Energy efficient design techniques for clock recovery in multilane receivers, receiver frontend in digital CDRs, reconfigurable voltage-mode transmitter, and PAM4 equalizer in full-duplex transceivers are discussed.
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Acknowledgement
The authors would like to acknowledge the Young Faculty Research Fellowship of Visvesvaraya PhD programme of MeitY for financial support in procuring soldering station that is used in populating our PCB boards for testing ICs developed during our research.
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Saxena, S. Wireline communication: the backbone of data transfer. CSIT 8, 147–156 (2020). https://doi.org/10.1007/s40012-020-00297-1
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DOI: https://doi.org/10.1007/s40012-020-00297-1