Skip to main content
SpringerLink
Log in

Power Saving Scheme for Process Corner Calibrated Standard Cell Based Flash ADC in Wireless Surveillance Applications

  • Original Research
  • Published:
SN Computer Science Aims and scope Submit manuscript

Abstract

This paper proposes a power saving scheme to be used in standard cell based Flash ADC for wireless surveillance applications. The input signal to the wireless surveillance network has a very low activity during night time as compared to day time. Thus, the input signal rarely reaches voltage greater than a reference voltage \(V_Z\). The reference voltage \(V_Z\) can be obtained by collecting a large number of light intensity samples during night time. The proposed power saving scheme uses an auxiliary standard cell comparator, whose switching threshold is kept equal to the reference voltage. The output of the auxiliary comparator disables a large number of comparator for all switching threholds greater than the reference voltage, thereby improving the power efficiency of the ADC. and simulated in a SCL 180 nm CMOS technology with a supply voltage of 1.8 V. The results show that the proposed design achieves an effective number of bits (ENOB) of 4.66 bits. The total power consumption of the proposed architecture using power saving scheme reduces at least by a factor of 2.5 in all the corners when compared to the existing standard cell based Flash ADC without power saving scheme.

This is a preview of subscription content, log in via an institution to check access.

Access this article

Log in via an institution

Price excludes VAT (USA)
Tax calculation will be finalised during checkout.

Instant access to the full article PDF.

Institutional subscriptions

Fig. 1
Fig. 2
Fig. 3
Fig. 4
Fig. 5
Fig. 6
Fig. 7
Fig. 8
Fig. 9
Fig. 10
Fig. 11
Fig. 12
Fig. 13

Similar content being viewed by others

References

  1. Wang Z, Chang MCF. A 600-MSPS 8-bit CMOS ADC using distributed track-and-hold with complementary resistor/capacitor averaging. IEEE Trans Circuits Syst I Regul Pap. 2008;55(11):3621–7.

    Article  MathSciNet  Google Scholar 

  2. Wong YL, Cohen MH, Abshire PA. A 750-MHz 6-b adaptive floating-gate quantizer in 0.35-\(\mu\)m CMOS. IEEE Trans Circuits Syst I Regul Pap. 2009;56(7):1301–12.

    Article  MathSciNet  Google Scholar 

  3. Yu H, Chang MCF. A 1-V 1.25-GS/S 8-bit self-calibrated flash ADC in 90-nm digital CMOS. IEEE Trans Circuits Syst II Express Briefs. 2008;55(7):668–72.

    Article  Google Scholar 

  4. Dominoni DM, Carmona-Wagner EO, Hofmann M, Kranstauber B, Partecke J. Individual-based measurements of light intensity provide new insights into the effects of artificial light at night on daily rhythms of urban-dwelling songbirds. J Anim Ecol. 2014;83(3):681–92.

    Article  Google Scholar 

  5. Sunil R, Siddharth RK, Nithin Kumar YB, Vasantha MH. An asynchronous analog to digital converter for video camera applications. In: IEEE computer society annual symposium on VLSI (ISVLSI), 2019, pp. 175–180.

  6. Wolf S. Silicon processing for the VLSI era: deep-submicron process technology. Sunset Beach. 2002.

  7. Park S, Palaskas Y, Flynn MP. A 4-GS/s 4-bit flash ADC in 0.18 nm CMOS. IEEE J Solid State Circuits. 2007;42:1865–72.

    Article  Google Scholar 

  8. Njinowa M, Siadjine M, Bui H, Boyer F. Design of low power 4 Bit Flash ADC based on standard cells. In: IEEE 11th international new circuits and systems conference (NEWCAS), 2013, pp. 1–4.

  9. Njinowa M, Bui H, Boyer F. Novel threshold based standard cell Flash ADC. Circuits Syst. 2012;3:29–34.

    Article  Google Scholar 

  10. Weaver S, Hershberg B, Moon U-K. Digitally synthesized stochastic Flash ADC using only standard digital cells. IEEE Trans Circuits Syst. 2014;61:84–91.

    Article  Google Scholar 

  11. Mayur SM, Siddharth RK , Nithin Kumar YB, Vasantha MH. Design of low power 4-bit 400MS/s standard cell based Flash ADC. In: IEEE computer society annual symposium on VLSI (ISVLSI), 2017, pp. 600–603.

  12. Khalapure Sumit, Siddharth RK, Nithin Kumar YB, Vasantha MH. Design of 5-bit flash ADC using multiple input standard cell gates for large input swing. In: IEEE computer society annual symposium on VLSI (ISVLSI), 2017, pp. 585–588.

  13. Mayur SM, Siddharth RK , Nithin Kumar YB, Vasantha MH. Design of low power 5-bit hybrid Flash ADC. In: IEEE computer society annual symposium on VLSI (ISVLSI), 2016, pp. 343–348.

  14. Yoo J, Choi K, Ghaznavi J. Quantum voltage comparator for 0.07 \(\mu\)m CMOS Flash A/D converters. In: IEEE computer society annual symposium on VLSI, 2013, pp. 135–139.

  15. Komar R, Bhat MS, Laxminidhi T. Switched inverter comparator based 0.5 V low power 6 bit flash ADC. IEEE Int Conf Semicond Electron (ICSE). 2012;613–617.

  16. Iyappan P, Jamuna P, Vijayasamundiswary S. Design of analog to digital converter using CMOS logic. Int Conf Adv Recent Technol Commun Comput. 2009;74–76.

  17. Pradeep R, Siddharth RK, Nithin Kumar YB, Vasantha MH. Process corner calibration for standard cell based Flash ADC. In: IEEE international symposium on smart electronic systems (iSES) (formerly iNiS), 2019, pp. 195–200.

Download references

Acknowledgements

This study was funded by SMDP-C2SD, Department of Electronics and Information Technology, Ministry of Electronics and IT, Government of India, (Grant Number MLA/MUM/GA/10(37)C).

Author information

Authors and Affiliations

  1. National Institute of Technology Goa, Ponda, India

    R. K. Siddharth, Y. B. Nithin Kumar & M. H. Vasantha

Authors
  1. R. K. Siddharth
    View author publications

    You can also search for this author in PubMed Google Scholar

  2. Y. B. Nithin Kumar
    View author publications

    You can also search for this author in PubMed Google Scholar

  3. M. H. Vasantha
    View author publications

    You can also search for this author in PubMed Google Scholar

Corresponding author

Correspondence to R. K. Siddharth.

Ethics declarations

Conflict of Interest

The authors declare that they have no conflict of interest.

Additional information

Publisher's Note

Springer Nature remains neutral with regard to jurisdictional claims in published maps and institutional affiliations.

This article is part of the topical collection “Technologies and Components for Smart Cities” guest edited by Himanshu Thapliyal, Saraju P. Mohanty, Srinivas Katkoori and Kailash Chandra Ray.

Rights and permissions

Reprints and permissions

About this article

Check for updates. Verify currency and authenticity via CrossMark

Cite this article

Siddharth, R.K., Kumar, Y.B.N. & Vasantha, M.H. Power Saving Scheme for Process Corner Calibrated Standard Cell Based Flash ADC in Wireless Surveillance Applications. SN COMPUT. SCI. 1, 310 (2020). https://doi.org/10.1007/s42979-020-00328-3

Download citation

  • Received:

  • Accepted:

  • Published:

  • DOI: https://doi.org/10.1007/s42979-020-00328-3

Keywords

Search

Navigation