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An Energy-efficient and High-speed Dynamic Comparator for Low-noise Applications

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Abstract

An energy-efficient, low-noise, and high-speed dynamic comparator is proposed in this work. The comparator uses two pre-amplifiers to have a two-stage operation for reduced kickback noise. It also incorporates the adaptive current reuse (ACR) technique for reduced latency and high-speed operation. The proposed comparator is designed and simulated in a 65-nm UMC CMOS process using a 1.2-V power supply. The performance of the design is verified using post-layout simulation and also through Monte Carlo simulations. The resultant offset standard deviation of 8 mV is observed, which is 3 times less compared to the conventional design. The maximum operating frequency of the comparator is 1 GHz. The worst-case energy consumption is 67 fJ with an average latency of 70 ps. The kickback noise of 5.5 mV is observed for the entire working range, which is almost 10 times less compared to the conventional dynamic comparator at 500 MHz clock frequency.

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  1. Department of Electrical Engineering, Indian Institute of Technology Jodhpur, Jodhpur, Rajasthan, India

    Bibhudutta Satapathy & Amandeep Kaur

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  1. Bibhudutta Satapathy
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  2. Amandeep Kaur
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Correspondence to Bibhudutta Satapathy.

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Satapathy, B., Kaur, A. An Energy-efficient and High-speed Dynamic Comparator for Low-noise Applications. Circuits Syst Signal Process 42, 5108–5120 (2023). https://doi.org/10.1007/s00034-023-02375-6

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  • DOI: https://doi.org/10.1007/s00034-023-02375-6

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