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Design of a low power and robust VLSI power line interference canceler with optimized arithmetic operators

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Abstract

The electric generator’s functional performance suffers from harmonic distortions such as first, second, and third-order. This work proposes a low power dissipation VLSI hardware architecture for a robust power line interference canceling (PLIC) in biopotential signals. Our proposed Least Mean Square (LMS) architecture presents just four clock cycles of latency per sample. The Harmonic Generator (HG) architectures are exploited and optimized in their arithmetic operations. We substituted conventional multipliers with adders and shifters and used efficient and previously published squarer units. In particular, the combination of radix-4 squarer unit and 3–2 subtractor compressor architecture is an efficient alternative for use in the HG. Our VLSI synthesis results show that combining the optimized adaptive filters LMS and HG’s hardware architecture, the proposed approach turns the PLIC VLSI structure robust and power-efficient. It effectively suppresses interferences in ECG (Electrocardiogram), EEG (Electroencephalogram), EMG (Electromyogram), and EOG (Electrooculogram) signals. Notably, the PLIC architecture is more efficient in the circuit area and power dissipation with the radix-4 and 3–2 subtractor compressor in the HG, saving up to 4.98 times in total power and 30.46% in the VLSI area, compared to the state-of-the-art solution.

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Data availability

The authors declare that the data supporting the findings of this study are available within the article. However, the data that support the findings of this study are available on request from the corresponding author M.M.A.R. (e-mail: mmarosa@inf.ufpel.edu.br).

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Acknowledgements

This work has been supported in part by FAPERGS under grant 19/2551-0001844-4 for funding.

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Authors and Affiliations

  1. Graduate Program on Electronic Engineering and Computing, Universidade Católica de Pelotas (UCPel), Pelotas, Brazil

    Morgana Macedo Azevedo da Rosa, Eduardo Antonio César da Costa & Sérgio J. M. Almeida

  2. Graduate Program in Microelectronics (PGMicro), Universidade Federal Do Rio Grande Do Sul (UFRGS), Porto Alegre, Brazil

    Patrícia Ücker da Costa, Guilherme Paim & Sergio Bampi

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  1. Morgana Macedo Azevedo da Rosa
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  2. Patrícia Ücker da Costa
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  3. Eduardo Antonio César da Costa
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Correspondence to Morgana Macedo Azevedo da Rosa.

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da Rosa, M.M.A., da Costa, P.Ü., da Costa, E.A.C. et al. Design of a low power and robust VLSI power line interference canceler with optimized arithmetic operators. Analog Integr Circ Sig Process 112, 247–261 (2022). https://doi.org/10.1007/s10470-022-02050-x

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