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Optimal Designs of Reversible/Quantum Decoder Circuit Using New Quantum Gates

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Abstract

The need for a low energy dissipation circuit in place of irreversible circuits at a fast pace. Among the emerging technology is quantum computing technology has attracted many advanced features such as information lossless and low energy dissipation. The need for reduction of quantum cost, quantum delay in the fundamental circuit like decoder is of prominent importance. The low quantum cost and quantum delay means fast computation in the quantum logic circuits. In this article, we have synthesized 2 − to − 4 decoder on three approaches based on S1G, S2G and S3G gates. Then we propose on two approaches a new design of 3 − to − 8 decoder as well as n − to − 2n decoder by cascading the proposed 2 − to − 4 decoder with a new gate called S4G, The proposed design of a novel 2 − to − 4 decoder (approach 3) can obtain superiority in terms of the number of Quantum cost, Quantum delay and garbage outputs (7,5 and 1respectively) compared with the existed circuits. Also we have designed a novel 3 − to − 8 decoder based on two approaches. Which is obvious on the low quantum delay of 15, quantum cost 23 and garbage output 1. In addition, various lemmas have presented to fix the quantum cost, quantum delay and garbage output for the design of n − to − 2n decoder. In the proposed 3 − to − 8 decoder design the rate of quantum cost, quantum delay and garbage outputs is 28%, 53% and 33% respectively less than the existing designs.

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References

  1. Landauer, R.: Irreversibility and heat generation in the computing process. IBM J. Res. Dev. 5, 183–191 (1961)

    Article  MathSciNet  Google Scholar 

  2. Bennett, C.H.: Logical reversibility of computation. IBM J. Res. Dev. 17, 525–532 (1973)

    Article  MathSciNet  Google Scholar 

  3. Nielsen, M.A., Chuang, I.L.: Quantum Computation and Quantum Information. Cambridge University Press, Cambridge (2000)

    MATH  Google Scholar 

  4. Kerntopf, P., Perkowski, M.A., Khan, M.H.A.: On universality of general reversible multiple valued logic gates Proceedings of the 34th IEEE International Symposium on Multiple Valued Logic, pp. 68–73 (2004)

  5. Smolin, J.A., DiVincenzo, D.P.: Five two-bit quantum gates are sufficient to implement the quantum Fredkin gate. Phys. Rev. A. 53, 2855–2856 (1996)

    Article  ADS  Google Scholar 

  6. Toffoli, T.: Reversible computing. Technical memo MIT/LCS/TM-151, MIT Laboratory for Computer Science (February) (1980)

  7. Fredkin, E., Toffoli, T.: Conservative logic. Int. J. Theor. Phys. 21, 219–253 (1982)

    Article  MathSciNet  Google Scholar 

  8. Peres, A.: Reversible logic and quantum computers. Phys. Rev. A. 32, 3266–3276 (1985)

    Article  ADS  MathSciNet  Google Scholar 

  9. Yu, P., Yafeng, Y., Jinzhao, L., Huawei, H., Wei, W.: An efficient method to synthesize reversible logic by using positive Davio decision diagrams. Circuits Syst. Signal Process. 33, 3107–3121 (2014)

    Article  MathSciNet  Google Scholar 

  10. Thapliyal, H., Ranganathan, N.: A New Reversible Design of BCD Adder, Design, Automation & Test in Europe Conference & Exhibition (DATE), 1–4 (2011)

  11. Misra, N.K., Sen, B., Wairya, S., Bhoi, B.: Testable novel parity-preserving reversible gate and low-cost quantum decoder design in 1D molecular-QCA. J. Circuits Syst. Comput. 26(09), 1750145 (2017)

  12. Feynman, R.: Quantum mechanical computers. Opt. News. 11–20 (1985)

  13. Surekha, M.: Efficient approaches for designing quantum costs of various reversible gates. Int. J. Eng. 9(1), 57–78 (2017)

    MathSciNet  Google Scholar 

  14. Slimani, A., Benslama, A.: The design of optimal reversible comparator circuit using new quantum gates. J. Phys. Conf. Ser.. IOP Publishing. 1, 1766 (2021)

    Google Scholar 

  15. Nagamani, A., Jayashree, H., Bhagyalakshmi, H.R.: Novel low power comparator design using reversible logic gates. Indian J. Comput. Sci. Eng. 2(4), 566–574 (2011)

    Google Scholar 

  16. Thapliyal, H., Vinod, A.P.: Design of Reversible Sequential Elements With Feasibility of Transistor Implementation. IEEE International Symposium on Circuits and Systems, 625–628 (2007)

  17. Ayyoub, S., Achour, B.: Optimized 4-bit quantum reversible arithmetic logic unit. Int. J. Theor. Phys. 56, 2686–2696 (2017)

    Article  Google Scholar 

  18. Zhou, R.G., Zhang, M.Q., Wu, Q., et al.: Optimization Approaches for Designing a Novel 4-Bit Reversible Comparator. Int. J. Theor. Phys. 52, 559–575 (2013)

    Article  Google Scholar 

  19. Lafifa, J., Masbaul, A., Hafiz, M., Hasan, B.: An efficient approach to design a reversible control unit of a processor. Sustain. Comput.: Inform. Syst. 3, 286–294 (2013)

  20. Michael, N., Nargarajan, R.: Design and analysis of a novel reversible encoder/Decoder.In:11th IEEE international conference on nanotechnology. (2011)

  21. Huda, N., Anwar, S., Jamal, L., Babu, H.M.H.: Design of a reversible random access memory. Dhaka Univ. J. Sci. 2(1), 31–38 (2011)

  22. Shamsujjoha, M., Babu, H.M.H.: A Low Power Fault Tolerant Reversible Decoder Using MOS Transistor, in: 26th International Conference on VLSI Design and the 12th International Conference on Embedded Systems, VLSID 2013, Pune, India, 368–373 (2013)

  23. Hari, S.K.S., Shroff, S., Mohammad, Sk. N., Kamakoti, V.: Efficient building blocks for reversible sequential circuit design. In: MWSCAS’06. 49th IEEE International Midwest Symposium on Circuits and Systems, Aug. 2006, 437–441 (2006)

  24. Maity, H., Biswas, A.: The Quantum Cost Optimized Design of 2: 4 Decoder Using the New Reversible Logic Block. Micro and Nanosystems. 146–148 (2020)

  25. Kannan, R., Vidhya, K.: Design of Combinational Circuits Using Reversible Decoder in Tanner tools. J. Comput. Theor. Nanosci. 17, 1743–1751 (2020)

    Article  Google Scholar 

Download references

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Authors and Affiliations

  1. University of Médéa Algeria, 26000, Médéa, Algeria

    Ayyoub Slimani

  2. Laboratoire de Physique Mathématique et Subatomique (LPMPS) Physics Department, Fundamental Sciences Faculty, Frères Mentouri University, 25000, Constantine, Algeria

    Achour Benslama

  3. Department of Electronics and Communication Engineering, Bharat Institute of Engineering and Technology, Hyderabad, 501510, India

    Neeraj Kumar Misra

Authors
  1. Ayyoub Slimani
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  2. Achour Benslama
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  3. Neeraj Kumar Misra
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Correspondence to Ayyoub Slimani.

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Slimani, A., Benslama, A. & Misra, N.K. Optimal Designs of Reversible/Quantum Decoder Circuit Using New Quantum Gates. Int J Theor Phys 61, 72 (2022). https://doi.org/10.1007/s10773-022-05017-w

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