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Gate-stack optimization of a vertically stacked nanosheet FET for digital/analog/RF applications

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Abstract

Nanosheet field effect transistors (NS-FET) are a most promising candidate for next-generation semiconductor devices for sub-7-nm technology nodes. This work explores a two-channel vertically stacked NS-FET from a digital and analog/RF perspective. The influence of high-κ gate oxide is investigated with respect to the NS-FET-based CMOS inverter and RF/analog parameters of the NS-FET. It is found that the high-κ gate oxide does not change the performance of the NS-FET-based CMOS inverter significantly. Moreover, the proposed NS-FET at LC = 12 nm exhibits Ion, Ion/Ioff, and subthreshold swing (SS) of 646 µA/µm, 1.24 × 107, and 68.8 mV/dec, respectively, for a SiO2 gate dielectric and 779 µA/µm, 2.5 × 107, and 70 mV/dec, respectively, for a TiO2 gate dielectric. However, the high-κ gate oxide leads to deterioration in RF/analog parameters of the NS-FET, particularly in weak/moderate regions of operation. To overcome the deterioration caused by the high-κ gate oxide, nanosheet thickness (TNS), channel length (LC), and spacer dielectric material are optimized. It is revealed that the degradation in RF/analog parameters can be reduced by considering a thicker TNS (10 nm), lower LC (8 nm), and low-κ spacer dielectric (SiO2).

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Authors and Affiliations

  1. Department of ECE, SR University, Warangal, Telangana, India

    Shubham Tayal, Sandip Bhattacharya, J. Ajayan & Laxman Raju Thoutam

  2. Department of ECE, NIT Raipur, Raipur, India

    Deboraj Muchahary

  3. Electronics Department, J. C. Bose University of Science & Technology YMCA, Faridabad, Haryana, India

    Sunil Jadav & Bal Krishan

  4. Department of ECE, Jamia Millia Islamia University, New Delhi, India

    M. Nizamuddin

Authors
  1. Shubham Tayal
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  2. Sandip Bhattacharya
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  3. J. Ajayan
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  4. Laxman Raju Thoutam
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  5. Deboraj Muchahary
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  6. Sunil Jadav
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  7. Bal Krishan
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  8. M. Nizamuddin
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Contributions

All the work in this paper was carried out together by Shubham Tayal, Sandip Bhattacharya, Deboraj Muchahary, J Ajayan, Laxman Raju Thoutam, Sunil Jadav, Bal Krishan and M. Nizamuddin.

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Correspondence to Shubham Tayal.

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Tayal, S., Bhattacharya, S., Ajayan, J. et al. Gate-stack optimization of a vertically stacked nanosheet FET for digital/analog/RF applications. J Comput Electron 21, 608–617 (2022). https://doi.org/10.1007/s10825-022-01864-2

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