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Impedance modeling and analysis of multi-stacked on-chip power distribution network in 3D ICs

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Abstract

An accurate impedance modeling of a multi-stacked on-chip power distributed network (PDN) based on through-silicon-vias (TSVs) is vitally important to estimate the electrical performance in three-dimensional integrated circuits (3D ICs). This paper proposes a method for calculating the impedance matrix of the multi-stacked on-chip PDN, which mainly consists of arbitrarily distributed TSVs and grid-type on-chip PDNs. First, a real stack-up structure of a multi-stacked on-chip PDN is separated into discrete components intentionally. Then, the equivalent lumped circuit models of all discrete components are assembled into a whole to build the transmission matrix of the multi-stacked on-chip PDN through the relationship between the nodal voltage and the nodal current. Finally, the impedance matrix can be derived through the transmission matrix. In this paper, the coupling of the arbitrarily distributed TSVs and the distributional effect of the on-chip PDN are considered in the impedance matrix through the transmission matrix method (TMM). The proposed method replaces the simulation of the complex equivalent circuit model with the matrix calculation. The verification results show that the deviation of resonant frequency is about 6\(\%\) and the conversation of the simulation time is about 99.9\(\%\) compared with the HFSS model. It can accurately and quickly calculate the impedance of the multi-stacked on-chip PDN.

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Acknowledgements

This research was supported in part by the National Natural Science Foundation of China (Grant Nos. 62021004, 61934006 and 61574106); and in part by the Industry University Research Project of Chongqing IC Innovation Research Institute, Xidian University (Grant No. CQIRI-2022CXY-05).

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Authors and Affiliations

  1. School of Microelectronics, Xidian University, Xi’an, 710071, China

    Yang Wang, Gang Dong, Wei Xiong, Dongliang Song, Zhangming Zhu & Yintang Yang

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  1. Yang Wang
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Correspondence to Gang Dong.

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Wang, Y., Dong, G., Xiong, W. et al. Impedance modeling and analysis of multi-stacked on-chip power distribution network in 3D ICs. J Comput Electron 21, 1282–1292 (2022). https://doi.org/10.1007/s10825-022-01947-0

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