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Tungsten work function engineering for dual metal gate nano-CMOS

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Abstract

A buffer layer technology for work function engineering of tungsten for dual metal gate Nano-CMOS is investigated. For the first time, tungsten is used as a p-type gate material using 1 nm of sputtered Aluminum Nitride (AlN x ) as a buffer layer on silicon dioxide (SiO2) gate dielectric. A tungsten work function of 5.12 eV is realized using this technology in contrast to a mid-gap value of 4.6 eV without a buffer layer. Device characteristics of a p-MOSFET on silicon-on-insulator (SOI) substrate fabricated with this technology are presented.

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Authors and Affiliations

  1. Advanced Microelectronic Center Aachen, AMO GmbH, Huyskensweg 25, 52074, Aachen, Germany

    J. K. Efavi, T. Mollenhauer, T. Wahlbrink, H. D. B. Gottlob, M. C. Lemme & H. Kurz

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  1. J. K. Efavi
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  2. T. Mollenhauer
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  3. T. Wahlbrink
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  4. H. D. B. Gottlob
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  5. M. C. Lemme
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  6. H. Kurz
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Correspondence to J. K. Efavi.

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Efavi, J.K., Mollenhauer, T., Wahlbrink, T. et al. Tungsten work function engineering for dual metal gate nano-CMOS. J Mater Sci: Mater Electron 16, 433–436 (2005). https://doi.org/10.1007/s10854-005-2310-8

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  • DOI: https://doi.org/10.1007/s10854-005-2310-8

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