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ASIP-based reconfigurable architectures for power-efficient and real-time image/video processing

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Abstract

To meet both flexibility and performance requirements, particularly when implementing high-end real-time image/video processing algorithms, the paper proposes to combine the application specific instruction-set processor (ASIP) paradigm with the reconfigurable hardware one. As case studies, the design of partially reconfigurable ASIP (r-ASIP) architectures is presented for two classes of algorithms with widespread diffusion in image/video processing: motion estimation and retinex filtering. Design optimizations are addressed at both algorithmic and architectural levels. Special processor concepts used to trade-off performance versus flexibility and to enable new features of post-fabrication configurability are shown. Silicon implementation results are compared to known ASIC, DSP or reconfigurable designs; the proposed r-ASIPs stand for their better performance–flexibility figures in the respective algorithmic class.

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Notes

  1. PSNR and bit-rate results in Table 1 are obtained using the H.264 JM 10 software model with maximum search displacement 16, five reference frames, seven variable block sizes. Tests include static videos as Akiyo and dynamic ones as Stefan (a Tennis scene), Mobile and Tennis Table.

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Acknowledgments

Discussions with Prof. G. Ramponi and Prof. S. Marsi, University of Trieste and Dr. D. Kammler and Dr. E. Witte, RWTH Aachen University, are gratefully acknowledged. The work has been partially supported by the European 6th FP Network of Excellence “Newcom” and the Integrated project “SHAPES”.

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Authors and Affiliations

  1. Department of Information Engineering, University of Pisa, Via Caruso 16, 56122, Pisa, Italy

    Sergio Saponara, Michele Casula & Luca Fanucci

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  1. Sergio Saponara
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  2. Michele Casula
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  3. Luca Fanucci
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Correspondence to Sergio Saponara.

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Saponara, S., Casula, M. & Fanucci, L. ASIP-based reconfigurable architectures for power-efficient and real-time image/video processing. J Real-Time Image Proc 3, 201–216 (2008). https://doi.org/10.1007/s11554-008-0084-y

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