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High-k Dielectric Double Gate Junctionless (DG-JL) MOSFET for Ultra Low Power Applications- Analytical Model

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Abstract

This paper describes the impression of low-k/high-k dielectric on the performance of Double Gate Junction less (DG-JL) MOSFET. An analytical model of the threshold voltage of DG-JLFET has been presented. Poisson’s equation is solved using the parabolic approximation to find out the threshold voltage. The effect of high-k on various performance parameters of N-type DG-JLFET is explored. The comparative analysis has been carried out between conventional gate oxide, multi oxide and high-k oxide in terms of Drain Induced Barrier Lowering (DIBL), threshold voltage, figure of merit (ION/IOFF) and sub-threshold slope (SS). The high-k oxide has shown superlative performance as compared to others. The results are further analyzed for various device structures. The DG-JLFET with HfO2 exhibits excellent attainment by mitigating the Short Channel Effects (SCEs). The significant reduction in off current makes the device suitable for ultra-low power applications. There is a 61.9 % and 34.29 % improvement in the figure of merit and sub-threshold slope in the proposed device as compared to other devices. The simulation of DG-JLFET is carried out using the Silvaco TCAD tool.

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Data Availability

The datasets generated and analyzed during the current study are not publicly available but may be available from the corresponding author on reasonable request.

Code Availability

The code used during this work is not available.

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Authors and Affiliations

  1. Department of Electronics & Communication Engineering, J.C. Bose University of Science & Technology, YMCA, Sector 6, Faridabad, 121006, India

    Prashant Kumar & Munish Vashishath

  2. Department of Electronics & Communication Engineering, Amity University Haryana, 122413, Gurugram, India

    Neeraj Gupta

  3. Department of Computer Science & Engineering, Amity University Haryana, 122413, Gurugram, India

    Rashmi Gupta

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  1. Prashant Kumar
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  2. Munish Vashishath
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  3. Neeraj Gupta
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  4. Rashmi Gupta
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Contributions

The idea of the research was conceptualized by Prashant Kumar and Neeraj Gupta carried out the analytical modeling and simulation of Junctionless MOSFET. The formal analysis and resources for the research were arranged by Munish Vashisht and Rashmi Gupta. Prashant Kumar also prepared the original draft of the paper and Neeraj Gupta did the review, proofreading and necessary editing in the article.

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Correspondence to Neeraj Gupta.

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Kumar, P., Vashishath, M., Gupta, N. et al. High-k Dielectric Double Gate Junctionless (DG-JL) MOSFET for Ultra Low Power Applications- Analytical Model. Silicon 14, 7725–7734 (2022). https://doi.org/10.1007/s12633-021-01525-2

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