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Impact of Drain Underlap and High Bandgap Strip on Cylindrical Gate All Around Tunnel FET and its Influence on Analog/RF Performance

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Abstract

This paper comprises of design and analysis of novel gate all around (GAA) cylindrical tunnel field effect transistor (TFET) using technology computer aided designing (TCAD) tool. The device designing incorporates drain underlap (DU) and high band-gap strip (HBS) at drain-channel junction. The purpose of DU is to minimize the drain induced influenced short channel effects (SCEs). While, the HBS is used to decrease the tunneling of carriers from channel-drain interface, which will result suppressed OFF-current \((I_{OFF})\). The analysis of analog/RF parameters of proffered TFET device is carried out in terms of drain current profile, subthreshold swing (SS), parasitic capacitance, transconductance \((g_m)\), cut-off frequency \((f_T)\), maximum oscillation frequency \((f_{max})\), and gain bandwidth (GBW).

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References

  1. Mertens H et al (2016) Gate-all-around MOSFETs based on vertically stacked horizontal Si nanowires in a replacement metal gate process on bulk Si substrates. IEEE Symp VLSI Technol:1–2. https://doi.org/10.1109/VLSIT.2016.7573416

  2. Kim S et al (2020) Investigation of electrical characteristic behavior induced by channel-release process in stacked nanosheet gate-all-around MOSFETs. IEEE Trans Electron Devices 67:2648–2652. https://doi.org/10.1109/TED.2020.2989416

    Article  CAS  Google Scholar 

  3. Saxena RS, Kumar MJ (2009) Stepped oxide hetero-material gate trench power MOSFET for improved performance. IEEE Trans Electron Devices 56:1355–1359. https://doi.org/10.1109/TED.2009.2019371

    Article  CAS  Google Scholar 

  4. Jaafar H, Aouaj A, Bouziane A, Iniguez B (2019) An analytical drain current model for cylindrical gate DMG-GC-DOT MOSFET. Int J Electron Lett 7:458–472. https://doi.org/10.1080/21681724.2018.1540058

    Article  Google Scholar 

  5. Wu J, Min J, Taur Y (2015) Short-channel effects in tunnel FETs. IEEE Trans Electron Devices 62:3019–3024. https://doi.org/10.1109/TED.2015.2458977

    Article  Google Scholar 

  6. Choi WY, Park B, Lee JD, Liu TK (2007) Tunneling field-effect transistors (TFETs) with subthreshold swing (SS) less than 60 mV/dec. IEEE Electron Device Letters 28:743–745. https://doi.org/10.1109/LED.2007.901273

    Article  CAS  Google Scholar 

  7. Jhan Y, Wu Y, Hung M (2013) Performance enhancement of nanowire tunnel field-effect transistor with asymmetry-gate based on different screening length. IEEE Electron Device Lett 34:1482–1484. https://doi.org/10.1109/LED.2013.2285156

    Article  CAS  Google Scholar 

  8. Vishvakarma SK, Beohar A, Vijayvargiya V, Trivedi P (2017) Analysis of DC and analog/RF performance on Cyl-GAA-TFET using distinct device geometry. J Semicond 38. https://doi.org/10.1088/1674-4926/38/7/074003

  9. Kim SH, Agarwal S, Jacobson ZA, Matheu P, Hu C, Liu TK (2010) Tunnel field effect transistor with raised Germanium source. IEEE Electron Device Lett 31:1107–1109. https://doi.org/10.1109/LED.2010.2061214

    Article  CAS  Google Scholar 

  10. Beohar A, Vishvakarma SK (2016) Performance enhancement of asymmetrical underlap 3D-cylindrical GAA-TFET with low spacer width IET. Micro Nano Lett 11:443–445. https://doi.org/10.1049/mnl.2016.0202

    Article  CAS  Google Scholar 

  11. Goswami PP, Bhowmick B (2020) Optimization of electrical parameters of pocket doped SOI TFET with L shaped gate. Silicon 12:693–700. https://doi.org/10.1007/s12633-019-00169-7

    Article  CAS  Google Scholar 

  12. Vimala P, Samuel TSA, Pandian MK (2020) Performance investigation of gate engineered tri-gate SOI TFETs with different high-K dielectric materials for low power applications. Silicon 12:1819–1829. https://doi.org/10.1007/s12633-019-00283-6

    Article  CAS  Google Scholar 

  13. Saurabh S, Kumar MJ (2009) Impact of strain on drain current and threshold voltage of nanoscale double gate tunnel field effect transistor: theoretical investigation and analysis. Jpn J Appl Phys 48. https://doi.org/10.1143/JJAP.48.064503

  14. Dharavath K, Vinod AA (2020) Two dimensional analytical model of heterostructure double gate with pocket doped tunnel FET. Silicon 12:1391–1397. https://doi.org/10.1007/s12633-019-00232-3

    Article  CAS  Google Scholar 

  15. Tayal S, Vibhu G, Meena S et al (2021) Optimization of device dimensions of high-k gate dielectric based DG-TFET for improved analog/RF performance. Silicon. https://doi.org/10.1007/s12633-021-01127-y

  16. Vijayvargiya V, Vishvakarma SK (2014) Effect of drain doping profile on double-gate tunnel field-effect transistor and its influence on device RF performance. IEEE Trans Nanotechnol 13:974–981. https://doi.org/10.1109/TNANO.2014.2336812

    Article  CAS  Google Scholar 

  17. Saurabh S, Kumar MJ (2011) Novel attributes of a dual material gate nanoscale tunnel field-effect transistor. IEEE Trans Electron Devices 58:404–410. https://doi.org/10.1109/TED.2010.2093142

    Article  CAS  Google Scholar 

  18. Saha P, Sarkhel S, Sarkar SK (2019) 3D modelling and performance analysis of dual material tri-gate tunnel field effect transistor. IETE Tech Rev 36:117–129. https://doi.org/10.1080/02564602.2018.1428503

    Article  Google Scholar 

  19. Phulawariya HK, Baidya A, Maity R et al (2021) Effects of hafnium oxide on short channel effects and DC analysis for double gate junctionless transistors. Trans Electr Electron Mater. https://doi.org/10.1007/s42341-021-00365-6

  20. Asthana PK, Goswami Y, Basak S, Rahi SB, Ghosh B (2015) Improved performance of a junctionless tunnel field effect transistor with a Si and SiGe heterostructure for ultra low power applications. RSC Adv 5(60). https://doi.org/10.1039/C5RA03301B

  21. Lp G, NB B (2020) Improvement of subthreshold characteristics of dopingless tunnel FET using hetero gate dielectric material: analytical modeling and simulation. Silicon 12:2189–2201. https://doi.org/10.1007/s12633-019-00314-2

    Article  CAS  Google Scholar 

  22. Choi WY, Lee W (2010) Hetero-gate-dielectric tunneling field-effect transistors. IEEE Trans Electron Devices 57:2317–2319. https://doi.org/10.1109/TED.2010.2052167

    Article  Google Scholar 

  23. Beohar A, Yadav N, Vishvakarma SK (2017) Analysis of trap assisted tunneling in asymmetrical underlap 3D-cylindrical GAA-TFET based on hetero-spacer engineering for improved device reliability. IET Micro Nano Lett 12:982–986. https://doi.org/10.1049/mnl.2017.0311

    Article  CAS  Google Scholar 

  24. Chattopadhyay A, Mallik A (2011) Impact of a spacer dielectric and a gate overlap/underlap on the device performance of a tunnel field-effect transistor. IEEE Trans Electron Devices 58:677–683. https://doi.org/10.1109/TED.2010.2101603

    Article  CAS  Google Scholar 

  25. Tiwari S, Dutt A, Joshi M, Nigam P, Mathew R, Beohar A (2021) Investigation of suppressed drain Cyl. GAA retrograde doped hetero-spacer steep density Film TFET. Springer J Comput Electron (accepted)

  26. Beohar A, Yadav N, Shah AP, Vishvakarma SK (2018) Analog/RF characteristics of a 3D Cyl underlap GAA-TFET based on a Ge-Source using fringing field engineering for low power applications. Springer J Comput Electron 17:1650–1657. https://doi.org/10.1007/s10825-018-1222-9

    Article  CAS  Google Scholar 

  27. Sentaurus device manual (2017) https://www.synopsys.com/silicon/tcad/sentausdevice.html

  28. Seabaugh AC, Zhang Q (2010) Low-voltage tunnel transistors for beyond CMOS logic. Proc IEEE 98:2095–2110

    Article  CAS  Google Scholar 

  29. Madan J, Chaujar R (2016) Interfacial charge analysis of hetero-geneous gate dielectric-gate all around-tunnel FET for improved device reliability. IEEE Trans Device Mater Reliability 16(2):227–234

    Article  CAS  Google Scholar 

  30. Zhang Q, Lu Y, Richter CA, Jena D, Seabaugh A (2014) Optimum bandgap and supply voltage in tunnel FETs. IEEE Trans Electron Devices 61:2719–2724. https://doi.org/10.1109/TED.2014.2330805

    Article  Google Scholar 

  31. Huang Q et al (2012) A novel Si tunnel FET with 36mV/dec subthreshold slope based on junction depleted-modulation through striped gate configuration. Int Electron Devices Meeting:851–854. https://doi.org/10.1109/IEDM.2012.6479005

  32. Chang H, Adams B, Chien P, Li J, Woo JCS (2013) Improved subthreshold and output characteristics of source-pocket Si tunnel FET by the application of laser annealing. IEEE Trans Electron Devices 60:92–96. https://doi.org/10.1109/TED.2012.2228006

    Article  CAS  Google Scholar 

  33. Walke AM et al (2014) Fabrication and analysis of a Si/Si0.55Ge0.45 heterojunction line tunnel FET. IEEE Trans Electron Devices 61:707–715. https://doi.org/10.1109/TED.2014.2299337

    Article  CAS  Google Scholar 

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Acknowledgements

Authors would like to thank VIT Bhopal University and VLSI Circuit & System Design Research Group, IIT Indore, Indore for providing the technical facilities for the completion of this work.

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Authors and Affiliations

  1. School of Electrical and Electronics Engineering (SEEE), VIT Bhopal University, M.P, 466114, Bhopal, India

    Arya Dutt, Sanjana Tiwari, Ribu Mathew & Ankur Beohar

  2. Chair for Electron Devices and Integrated Circuits, Technische Universität Dresden, Dresden, 01069, Germany

    Abhishek Kumar Upadhyay

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  1. Arya Dutt
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  2. Sanjana Tiwari
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  3. Abhishek Kumar Upadhyay
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  4. Ribu Mathew
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  5. Ankur Beohar
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All the authors (Arya Dutt, Sanjana Tiwari, Abhishek Kumar Upadhyay, Ribu Mathew,Ankur Beohar) have equal contribution.

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Correspondence to Ankur Beohar.

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Dutt, A., Tiwari, S., Upadhyay, A.K. et al. Impact of Drain Underlap and High Bandgap Strip on Cylindrical Gate All Around Tunnel FET and its Influence on Analog/RF Performance. Silicon 14, 9789–9796 (2022). https://doi.org/10.1007/s12633-022-01692-w

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