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Implementation and Performance Evaluation of Ferroelectric Negative Capacitance FET

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Abstract

With the constant increase in power dissipation of nanoscale transistors, the almost four-decade-old cycle of performance advancement in complementary metal–oxide–semiconductor (CMOS) technology is in danger of being disrupted. As revealed in the first study, negative capacitance states in an isolated ferroelectric capacitor can be identified almost instantly when the capacitor is switched on. Increasing ferroelectric volume fraction depolarization, as demonstrated by phase-field modelling, results in rapid expansion of domain walls, which results in a negative capacitance signature. One must understand how the ferroelectric material is connected to the interfacial oxide and semiconductor, as well as how negative capacitance values can be achieved, in order to obtain amplification and margin of error. If one can adhere to these guidelines, your design will be optimized and free of hysteresis issues. The negative capacitance effect of ferroelectric oxides, according to our research, can be leveraged to drastically minimize power dissipation in nanoscale semiconductor transistors. The SS can be reduced to less than 60 mV/dec by using FETs with negative capacitance, such as FE-FETs and other comparable devices. These FETs' gate dielectric is comprised of an unstable substance, making them unstable.

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Acknowledgements

The authors are thankful to Gokaraju Rangaraju Institute of Engineering & Technology, Hyderabad for their cooperation and support during this research work.

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Authors and Affiliations

  1. Department of EIE, Bannari Amman Institute of Technology, Sathyamangalam, Erode, Tamil Nadu, 638401, India

    R. Deepa

  2. Department of ECE, Velalar College of Engineering and Technology, Erode, Tamil Nadu, 638012, India

    M. Parimala Devi

  3. Department of ECE, Gokaraju Rangaraju Institute of Engineering and Technology, Hyderabad, 500090, Telangana, India

    N. Arun Vignesh

  4. Department of ECE, MVJ College of Engineering, Bengaluru, India

    S. Kanithan

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  1. R. Deepa
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  2. M. Parimala Devi
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  4. S. Kanithan
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Contributions

R Deepa, M.Parimala Devi, N Arun Vignesh and S Kanithan: Conceptualization; R Deepa, M.Parimala Devi, and N Arun Vignesh: investigation; R Deepa, M.Parimala Devi, N Arun Vignesh and S Kanithan: resources; R Deepa, M.Parimala Devi, N Arun Vignesh and S Kanithan: data curation; R Deepa, M.Parimala Devi, N Arun Vignesh and S Kanithan: writing—original draft preparation; R Deepa, M.Parimala Devi, N Arun Vignesh and S Kanithan: writing—review and editing; R Deepa, M.Parimala Devi, N Arun Vignesh and S Kanithan: visualization; R Deepa: supervision.

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Correspondence to R. Deepa.

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Deepa, R., Devi, M.P., Vignesh, N.A. et al. Implementation and Performance Evaluation of Ferroelectric Negative Capacitance FET. Silicon 14, 2409–2419 (2022). https://doi.org/10.1007/s12633-022-01722-7

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  • DOI: https://doi.org/10.1007/s12633-022-01722-7

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