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Design and Optimization of Dual Material Gate Junctionless FinFET Using Dimensional Effect, Gate Oxide and Workfunction Engineering at 7 nm Technology Node

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Abstract

In this paper, we designed and analyzed the performance of Dual Material Gate Junctionless FinFET(DMG JLFinFET) using gate engineering with high-k dielectrics for nanoscale applications. Here first we optimized the doping and later optimized the work function. Thereafter by using these optimized values we carried our work for other simulations. Various high-k materials are used as gate oxide. We found that by replacing gate oxide with high-k materials the device performance is improved in terms of Ion/Ioff, SS, and DIBL. The fine tuning of gate workfunction reduces short channel effects (SCEs). In Fin width (FW) variation, single gate oxide HfO2 has 61.29 mV/dec and 16.03 mV/V, dual gate-oxide Si3N4 + HfO2 has 61.22 mV/dec and 18.49 mV/V as SS and DIBL, respectively. In Fin height (FH) variation single gate oxide HfO2 has 63.04 mV/V and 27.11 mV/V, dual gate oxide Si3N4 + HfO2 has 62.57 mV/V and 26.05 mV/V as SS and DIBL, respectively. Ion/Ioff is improved to 0.78 × 107 using HfO2 and 1.25 × 107 using Si3N4 + HfO2 as gate oxides. The ratio of Ion/Ioff with FH and FW variation provide evidence that the DMG JLFinFET is best competent for low power nanoscale applications. 3-D simulations are done using Cogenda genius Visual TCAD.

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Acknowledgements

The authors thank to the Department of Electronics and Communications Engineering, NIT Warangal for providing the TCAD Tools.

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  1. Department of Electronics and Communication Engineering, National Institute of Technology Warangal, Warangal, 506004, India

    Rambabu Kusuma & V. K. Hanumantha Rao Talari

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  1. Rambabu Kusuma
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  2. V. K. Hanumantha Rao Talari
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Contributions

Rambabu Kusuma: Writing- Original draft preparation, Formal Analysis, Investigation,Simulation, Data Curation. VK Hanumantha Rao Talari: Conceptualization, Methodology, Supervision.

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Correspondence to Rambabu Kusuma.

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Kusuma, R., Talari, V.K.H.R. Design and Optimization of Dual Material Gate Junctionless FinFET Using Dimensional Effect, Gate Oxide and Workfunction Engineering at 7 nm Technology Node. Silicon 14, 10301–10311 (2022). https://doi.org/10.1007/s12633-022-01769-6

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