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Optimization of Design Space for Vertically Stacked Junctionless Nanosheet FET for Analog/RF Applications

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Abstract

This paper investigates the various device dimensions such as gate length (Lg), nanosheet thickness (TNS), and nanosheet width to optimize the design space for vertically stacked Junctionless Nanosheet Field Effect Transistor (JL-NSFET). The optimization has been carried out by considering several analog/RF parameters that include On-current (ION), Off-current (IOFF), Transconductance Efficiency (gm/Id), Subthreshold Swing (SS), Drain Induced Barrier Lowering (DIBL), ION/IOFF ratio, Transconductance (gm), gate capacitance (Cgg), Output conductance (gds), and Cutoff-frequency (fT), Intrinsic gain (Av) are explored here. It is found that the downscaling of Lg from 16 nm to 8 nm resulted in an increase in SS and DIBL. However, scaling down of TNS (WNS) from 10 nm to 5 nm (from 18 nm to 10 nm) resulted in a decrease in SS by ~30.5% (~16.39%) and in DIBL by ~44.23% (~78.59%) respectively. The short channel effects (SCE) are greatly suppressed by upscaling of Lg and downscaling of TNS and WNS. The transconductance (gm) is improved by decreasing the Lg and TNS but a significant degradation is found for WNS. Further, the gain (Av) is improved by an amount of ~22.86% by upscaling the Lg and ~ 7.07%, ~31.75% with the downscaling of TNS and WNS respectively. The gate capacitances (Cgg) are reduced with the downscaling of Lg and WNS, however the same is increased for TNS. Moreover, the cutoff frequency (fT) is improved with scaling down of Lg and TNS in comparison with the WNS.

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Acknowledgements

The authors would like to thank Dr. Sayan Kanungo, BITS Pilani, Hyderabad Campus for providing us the facility to simulate this work using Sentaurus TCAD tools.

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  1. Department of Electronics and Communication Engineering, SR University, Warangal, India

    Sresta Valasa, Shubham Tayal & Laxman Raju Thoutam

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  1. Sresta Valasa
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All the works (Conceptualization, Methodology, Writing Original Draft, Software, Validation and Investigation, Formal analysis, Resources, Data Curation, Writing Review and Editing) in this paper have done together by Sresta Valasa, Shubham Tayal, Laxman Raju Thoutam.

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Correspondence to Sresta Valasa.

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Valasa, S., Tayal, S. & Thoutam, L.R. Optimization of Design Space for Vertically Stacked Junctionless Nanosheet FET for Analog/RF Applications. Silicon 14, 10347–10356 (2022). https://doi.org/10.1007/s12633-022-01793-6

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