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Effect of Temperature on Performance of 5-nm Node Silicon Nanosheet Transistors for Analog Applications

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Abstract

This work investigates the effects of temperature on the performance of a 5-nm node N-channel Nanosheet Transistor (NST) for analog applications. A fully calibrated commercial TCAD platform is used for the device as well as mixed-mode circuit simulations. The range of temperature used in the study is from 250 to 450 K. The transconductance (gm) of the NST shows a change in the sign of its temperature coefficient (TC), from positive to negative, around a gate voltage of 0.52 V. The Output-conductance (gds) and Early-voltage (VEA) parameters increase with the increase in temperature. However, the Intrinsic-gain (Av), Transconductance-generation-efficiency (gm/IDS), Unit-gain-frequency (fT), Gain-Frequency product (GFP), Transconductance–Frequency product (TFP), and Gain- Transconductance–Frequency product (GTFP) parameters are observed to deteriorate with the increasing temperature. For the increase in temperature from 250 to 450 K: the maximum gm value is seen to decrease from 228 µS to 200 µS; the gds values increase from 24.6 µS to 27.1 µS; the early voltage (at VGS = 400 mV) improves from 2.37 to 2.71 V; the fT value decreases from 568 GHz to 524 GHz; the Av value falls from 9.2 to 7.4; Discharge-time (td) value improves from 9.45 ns to 8.11 ns; the gm/IDS values degrade from 37.5 V− 1 to 22.4 V− 1; the GFP value falls from 5.22 THz to 3.86 THz.

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Authors and Affiliations

  1. National Institute of Technology Uttarakhand, Srinagar Garhwal, Uttarakhand, 246174, India

    Yogendra Pratap Pundir, Arvind Bisht, Rajesh Saha & Pankaj Kumar Pal

  2. Hemvati Nandan Bahuguna Garhwal University, Srinagar Garhwal, Uttarakhand, 246174, India

    Yogendra Pratap Pundir

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  1. Yogendra Pratap Pundir
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  2. Arvind Bisht
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  3. Rajesh Saha
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  4. Pankaj Kumar Pal
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Contributions

Yogendra Pratap Pundir has contributed in the Conceptualization, Methodology, Writing Original Draft, Software, Data Curation and Investigation. Rajesh Saha and Arvind Bisht have contributed to the Formal analysis. Pankal Kumar Pal has contributed to Formal analysis and Editing of this paper.

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Correspondence to Yogendra Pratap Pundir.

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Pundir, Y.P., Bisht, A., Saha, R. et al. Effect of Temperature on Performance of 5-nm Node Silicon Nanosheet Transistors for Analog Applications. Silicon 14, 10581–10589 (2022). https://doi.org/10.1007/s12633-022-01800-w

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