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Improved Drain Current with Suppressed Short Channel Effect of p + Pocket Double-Gate MOSFET in Sub-14 nm Technology Node

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Abstract

Low dimension and low power consumption are major parameters of concern for transistor-level design. Multi-gate MOSFET is one of the potential transistors showing better subthreshold performance that is suitable for low power VLSI design. In this paper, a p + pocket double gate MOSFET is designed with 14 nm gate length using gate engineering and channel engineering techniques to achieve improvement in subthreshold performance. The addition of pocket region results in enhanced barrier subthreshold conduction in transistor OFF-state condition with negligible effect on ON-state current. Pocket region length is also varied from 3 to 5 nm for performance enhancement. The paper mainly covers the DC analysis of proposed p + pocket DGMOSFET for calculation of subthreshold parameters such as ON/OFF current ratio, subthreshold slope and DIBL values. The proposed DGMOSFET shows steep subthreshold performance with ON/OFF current ratio (~ 1010), subthreshold slope (< 60mV/V) and negligible DIBL values. 2-D visualization of the proposed transistor is extracted in terms of channel electron density, energy band diagram, electrostatic potential and electric field etc. The transistor performance is also evaluated for temperature variations ranging from 250 to 400 K in steps of 25 K that show the reliability of the transistor in varying operating conditions. Material engineering is applied for the performance enhancement of the proposed p + pocket DGMOSFET with the different channel, gate and oxide materials. A similar p-channel transistor is also explored for future CMOS-based logic and memory applications. The transistor design and performance evaluation are carried out using TCAD 2D/3D device simulator by Cogenda.

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Data Availability

The associated data will be made available on request.

Code Availability

The proposed device is designed and simulated on Visual TCAD.

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Acknowledgements

We acknowledge for the support and lab facility provided by department of VLSI design, School of Electronics and Electrical Engineering, Lovely Professional University, Punjab India.

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Authors and Affiliations

  1. School of Electronics and Electrical Engineering, Lovely Professional University, Jalandhar, India

    Suman Lata Tripathi, Abhishek Kumar & Sobhit Saxena

  2. GLA University, Mathura, India

    Pooja Pathak

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  1. Suman Lata Tripathi
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  2. Pooja Pathak
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  3. Abhishek Kumar
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Correspondence to Suman Lata Tripathi.

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Tripathi, S.L., Pathak, P., Kumar, A. et al. Improved Drain Current with Suppressed Short Channel Effect of p + Pocket Double-Gate MOSFET in Sub-14 nm Technology Node. Silicon 14, 10881–10891 (2022). https://doi.org/10.1007/s12633-022-01816-2

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