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Analysis and Design of Novel Doping Free Silicon Nanotube TFET with High-density Meshing Using ML for Sub Nanometre Technology Nodes

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Abstract

Beyond the 25 nm technological node, MOSFETs (metal oxide semiconductor FETs) have worse channel electrostatic control than FinFETs (Fin field-effect transistors). It is necessary to use novel gate and channel engineering architecture in MOSFET devices at low technology nodes to decrease short-channel effects (SCEs). Future nano devices will replace present MOSFET with graded channel double gate MOSFETs and FinFETs for increased ION current and reduced leakage currents. Double gate MOSFETs have been identified by researchers in the last few years to considerably reduce short channel effects (SCE). Graded channel double gate MOSFETs provide superior switching characteristics and higher transconductance than single gate MOSFETs in ULSI/VLSI applications with many nodes. Transistors with hot carrier effects and subthreshold properties degrade at lower technological nodes than 25 nm. To increase on-state drive current and off-state leakage current separately in the gate-to-channel direction, super-halo and retrograde channel doping are used. As a result, semiconductor businesses must place a premium on precise doping levels, which drives up fabrication costs enormously. A revolutionary doping-free Silicon nanotube FET (DF-Si-NT-FET) with sub-nm technology nodes is presented in this paper. They are extremely resistant to SCE due to the strong charge control offered by both the inner and outside channels. Also, machine learning (ML) algorithm used with high-density meshing during simulation. TCAD was used to create all the simulations for this work.

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Acknowledgements

The authors are thankful to Gokaraju Rangaraju Institute of Engineering & Technology, Hyderabad for their cooperation and support during this research work.

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Authors and Affiliations

  1. Department of ECE, Jaypee University of Engineering and Technology, Guna, 473226, India

    Ravi Kumar

  2. Department of ECE, Dr. N.G.P Institute of Technology, Dr. N.G.P. Nagar, Kalapatti Road, Coimbatore, Tamil Nadu, 641048, India

    B. Aruna Devi

  3. Department of CSE, Geethanjali Institute of Science and Technology, Nellore, 524137, Andhra Pradesh, India

    V. Sireesha

  4. Department of ECE, Andhra Engineering College, Nellore, 524322, Andhra Pradesh, India

    A. Kishore Reddy

  5. Department of Micro and Nano Electronics Engineering, School of Electronics Engineering, Vellore Institute of Technology, 632014, Vellore, India

    I. Hariharan

  6. Department of Embedded Technology, School of Electronics Engineering, Vellore Institute of Technology, Vellore, 632014, India

    E. Konguvel

  7. Department of ECE, GRIET, 500090, Hyderabad, Telangana, India

    N. A Vignesh

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  1. Ravi Kumar
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  2. B. Aruna Devi
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  7. N. A Vignesh
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Contributions

Ravi Kumar, B Aruna Devi, and N. A Vignesh: Conceptualization; I. Hariharan, E. Konguvel, and N. A Vignesh: investigation; A.Kishore Reddy, I. Hariharan, and N. A Vignesh : resources; Ravi Kumar, B Aruna Devi, V. Sireesha, A.Kishore Reddy, and N. A Vignesh: data curation; Ravi Kumar, I. Hariharan, E. Konguvel, and N. A Vignesh: writing—original draft preparation; V. Sireesha, A.Kishore Reddy, I. Hariharan, and N. A Vignesh: writing—review and editing; Ravi Kumar, B Aruna Devi, V. Sireesha, A.Kishore Reddy, I. Hariharan, E. Konguvel, and N. A Vignesh: visualization; N. A Vignesh: supervision.

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Correspondence to N. A Vignesh.

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Author(s): N Arun Vignesh.

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Kumar, R., Devi, B.A., Sireesha, V. et al. Analysis and Design of Novel Doping Free Silicon Nanotube TFET with High-density Meshing Using ML for Sub Nanometre Technology Nodes. Silicon 14, 11235–11242 (2022). https://doi.org/10.1007/s12633-022-01859-5

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