Elsevier

Computer Communications

Volume 12, Issue 6, December 1989, Pages 337-348
Computer Communications

Proposed high speed packet switch for broadband integrated networks

https://doi.org/10.1016/0140-3664(89)90004-2Get rights and content

Abstract

The design of a high speed, broadband packet switch with two priority levels for application in integrated voice/data networks is presented. The packet switch can efficiently cope with 128 byte packets converging on it from eight 140 Mbit/s dynamic time division multiplexed fibre optic links. The packet switch throughput varies with the load and traffic composition, and the delay experienced by voice and data packets is within 300 μs and 3 ms, respectively. The design is implemented by task-sharing in a multi-processor configuration. The design of the packet switch, including its subsystems, is detailed here.

References (13)

  • PE White et al.

    Switching systems for broadband networks

    IEEE J. Selected Areas of Commun.

    (October 1987)
  • JY Hui et al.

    A broadband packet switch for integrated transport

    IEEE J. Selected Areas of Commun.

    (October 1987)
  • YS Yeh et al.

    The knockout switch: a simple, modular architecture for high performance packet switching

    IEEE J. Selected Areas of Commun.

    (October 1987)
  • S Nojima et al.

    Integrated services packet network using bus matrix switch

    IEEE J. Selected Areas of Commun.

    (October 1987)
  • GJ Coviello

    Comparative discussion of circuit vs packet switched voice

    IEEE Trans. Commun.

    (August 1979)
  • MA Sencer et al.

    A viewpoint on packet switched voice networks

There are more references available in the full text version of this article.

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