New cascaded multilevel inverter topology with minimum number of switches

https://doi.org/10.1016/j.enconman.2009.06.032Get rights and content

Abstract

In this paper, a new topology of cascaded multilevel inverter using a reduced number of switches, insulated gate driver circuits and voltage standing on switches is proposed. The proposed topology results in reduction of installation area and cost and has simplicity of control system. This structure consists of series connected sub-multilevel inverters blocks. Three algorithms for determination of magnitudes of dc voltage sources have been presented, too. Validity of the analysis has been proved by simulation and experimental results.

Introduction

A multilevel inverter is a power electronic system that synthesizes a desired output voltage from several levels of dc voltages as inputs. Recently, multilevel power conversion technology has been developing the area of power electronics very rapidly with good potential for further developments. The most attractive applications of this technology are in the medium to high voltage ranges.

The concept of utilizing multiple small voltage levels to perform power conversion was presented by a MIT researcher [1], [2]. Advantages of this multilevel approach include good power quality, good electro-magnetic compatibility, low switching losses and high voltage capability.

The first introduced topology is the series H-bridge design [1]. This was followed by the diode-clamped inverter [2], [3], [4] which utilizes a bank of series capacitors to split the dc bus voltage. The flying-capacitor (or capacitor clamped) [5] topology followed diode-clamped after few years, instead of series connected capacitors, this topology uses floating capacitors to clamp the voltage levels. Another multilevel design, slightly different from the previous one, involves parallel connection of inverter phases through inter-phase reactors [6]. In this design the semiconductors must block the entire voltage, but share the load current. Also, several combinatorial designs have emerged [7], implemented cascading the fundamental topologies [8], [9], [10], [11], [12]; they are called hybrid topologies. These designs can create power quality for a given number of semiconductor devices higher than the fundamental topologies alone due to a multiplying effect of the number of levels [13]. Also, some soft-switching methods can be implemented for different multilevel inverters to reduce the switching loss and to increase efficiency [14], [15]. Recently, several multilevel inverter topologies have been developed [16], [17], [18], [19].

Unfortunately, multilevel inverters have some disadvantages. One particular disadvantage is the great number of power semiconductor switches needed. Although low voltage rate switches can be utilized in a multilevel inverter, each switch requires a related gate driver circuits. This may cause the overall system to be more expensive and complex. So, in practical implementation, reducing the number of switches and gate driver circuits is very important.

This paper suggests a new topology for cascaded multilevel inverters with a high number of steps associated with a low number of switches and gate driver circuits for switches. In addition, for producing all levels (odd and even) at the output voltage, three procedures for calculating the required dc voltage sources are proposed. Finally, the paper includes simulation and experimental results to prove the feasibility of the proposed multilevel inverter.

Section snippets

Conventional cascaded multilevel inverters

The full-bridge topology with four switches is used to synthesize a three-level square-wave output voltage waveform. The cascaded multilevel inverter consists of series connections of n full-bridge topology. Fig. 1 shows the configuration of cascaded multilevel inverter. The overall output voltage of multilevel inverter is given by:vo=vo,1+vo,2++vo,n

If all dc voltage sources in Fig. 1 equal to Vdc, the inverter is known as symmetric multilevel inverter. The effective number of output voltage

Suggested topology

Fig. 2 shows the suggested basic unit for a sub-multilevel inverter. This consists of a capacitor (with dc voltage equal to Vdc) with two switches S1 and S2. Table 1 indicates the values of vo for states of switches S1 and S2. It is clear that both switches S1 and S2 can not be on simultaneously because a short circuit across the voltage Vdc would be produced. It is noted that two values can be achieved for vo. The basic unit shown in Fig. 2 can be cascaded as shown in Fig. 3.

Although this

Extended structure

The multilevel proposed in Fig. 3, only can generate the positive output voltages. For generating both of the positive and negative output voltages, the structure shown in Fig. 5 is proposed. In this figure, the full-bridge topology added to the output terminals of the circuit shown in Fig. 3. The direction of load current and voltage are as shown in Fig. 5. It is clear that both switches S1 and S4 (or S2 and S3) can not be on simultaneously because a short circuit across the voltage vo

Comparison of the suggested structure with conventional cascaded multilevel inverter

The main purpose of this paper is reduction of the components of the cascaded multilevel inverters. Each switch in the suggested topology is composed of one insulated-gate bipolar transistor (IGBT) and one anti-parallel diode. Also, each switch requires one gate driver as shown in Fig. 7. Fig. 7 shows the isolator and driver circuit of each switch. This circuit consists of an opto-isolator, a schmit trigger and a buffer. Each switch in the inverter requires an isolated driver circuit. The

Simulation and experimental results

To examine the performance of the proposed multilevel inverter in the generation of a desired output voltage waveform, a prototype is simulated and implemented based on the proposed topology according to that one shown in Fig. 11. The PSCAD software has been used for simulation. The multilevel shown in Fig. 11 is a 11-level multilevel inverter and can generate staircase waveform with maximum 100 V on output. The load is a series R–L with magnitudes 70 Ω and 55 mH, respectively.

There are several

Conclusions

A new configuration of cascaded multilevel inverter has been proposed. The suggested topology needs fewer switches and gate driver circuits with minimum standing voltage on switches for realizing Nstep for the load. Therefore, the proposed topology results in reduction of installation area and cost and has simplicity of control system. Also, three procedures have been presented for determination of the magnitudes of the dc voltage sources. The operation and performance of the proposed

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