Review of multilevel voltage source inverter topologies and control schemes
Introduction
The preliminary studies on multilevel inverters (MLI) have been performed using three-level inverter that has been proposed by Nabae. In the study, the third level has been constituted by using neutral point of DC line and the topology has been defined as diode clamped MLI (DC-MLI) [1], [2]. In recent years, multilevel inverters have gained much attention in the application areas of medium voltage and high power owing to their various advantages such as lower common mode voltage, lower voltage stress on power switches, lower dv/dt ratio to supply lower harmonic contents in output voltage and current. Comparing two-level inverter topologies at the same power ratings, MLIs also have the advantages that the harmonic components of line-to-line voltages fed to load are reduced owing to its switching frequencies. The most common MLI topologies classified into three types are diode clamped MLI (DC-MLI), flying capacitor MLI (FC-MLI), and cascaded H-Bridge MLI (CHB-MLI). The hybrid and asymmetric hybrid inverter topologies have been developed according to the combination of existing MLI topologies or applying different DC bus levels respectively [3], [4], [5], [6], [7], [8], [9]. The basic topologies of MLIs are shown in Fig. 1. The recent applications of MLIs have a variety including induction machine and motor drives, active rectifiers, filters, interface of renewable energy sources, flexible AC transmission systems (FACTS), and static compensators. The diode clamped inverters, particularly the three-level structure, have a wide popularity in motor drive applications besides other multilevel inverter topologies. However, it would be a limitation of complexity and number of clamping diodes for the DC-MLIs, when the level exceeds three [10], [11], [12], [13]. The FC-MLIs are based on balancing capacitors on phase buses and generate multilevel output voltage waveform clamped by capacitors instead of diodes. The FC-MLI topology also requires balancing capacitors per phase at a number of (m − 1) · (m − 2)/2 for an m-level inverter and it will cause to increase the number of required capacitor in high level inverter topologies and complexity of considering DC-link balancing.
Among the three types of multilevel inverters, the cascade inverter has the least components for a given number of levels. Cascade multilevel inverters consists of a series of H-bridge cells to synthesize a desired voltage from several separate DC sources (SDCSs) which may be obtained from batteries or fuel cells. All these properties of cascade inverters allow using various pulse width modulation (PWM) strategies to control the inverter accurately [13], [14], [15], [16], [17]. In addition to these topologies, several modulation and control techniques have been developed for multilevel inverters including selective harmonic elimination PWM (SHE-PWM), sinusoidal PWM (SPWM), space vector PWM (SVM), and similar variations of the three main algorithms. The modulation methods used in multilevel inverters can be classified according to switching frequencies as seen in Fig. 2 [18], [19], [20], [21].
The SPWM control method is very popular in industrial applications owing to its harmonic reducing opportunities by using several phase shifting options on carrier signal. In the SPWM, a sinusoidal reference voltage waveform is compared with a triangular carrier waveform to generate gate signals for the switches of inverter. Several multicarrier techniques have been developed to reduce the THD ratios, based on the classical SPWM with triangular carriers. Another alternative modulation technique is SVM strategy, which has been used appropriately in three-level inverters. The SVM and SHE-PWM methods are fundamental frequency switching methods and perform one or two commutations of the power semiconductors during one cycle of the output voltages to generate a staircase waveform [22], [23], [24], [25], [26].
This paper presents the multilevel inverter topologies and their control methods according to existing and novel applications, based on a well-surveyed literature summary. A comprehensive study has been performed on common and hybrid multilevel inverters, and the most appropriate control schemes and applications have been proposed according to topologies.
Section snippets
Common inverter topologies
Three major multilevel inverter structures which have been mostly applied in industrial applications have been emphasized as the diode clamped, the flying capacitor, and the cascaded H-bridge inverters with separate DC sources. In addition to this, various hybrid multilevel inverters have been developed by using the three basic types mentioned above. Voltage source inverters (VSIs) are widely used in AC motor drives, AC uninterruptible power supplies (UPS), and AC power supplies with batteries,
Control schemes
The efficiency parameters of a multilevel inverter such as switching losses and harmonic reduction are principally depended on the modulation strategies used to control the inverter. As depicted in Fig. 2, multilevel inverter control techniques are based on fundamental and high switching frequency. Another widely used popular classification for the modulation methods developed to control the multilevel inverters is depend upon open loop and closed loop concepts as depicted in Fig. 8. Three main
Comparison of the topologies and control scheme
The most common multilevel inverter topologies and control schemes have been reviewed in this paper. As mentioned in Section 1, the multilevel concept has been introduced with a diode clamped topology in 1980s by Nabae. MLIs are increasingly being used in medium voltage and high power applications owing to numerous advantages such as low power dissipation due to reducing the voltage stress on switching devices and minimizing the harmonic contents at the output of the inverter. The selected
Conclusions
Based on the survey of conventional multilevel inverter topologies given in the previous sections, general and asymmetrically constituted H-MLIs have been also reviewed in this paper. Many new hybrid topologies can be designed through the combinations of three main MLI topologies. Besides the combination of topologies, the trade-offs in MLI structures can be dealt by using AH-MLIs that is formed using different DC source levels in inverter cells. Nevertheless, conventional PWM strategies that
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