Elsevier

Microelectronic Engineering

Volume 88, Issue 11, November 2011, Pages 3312-3315
Microelectronic Engineering

Accelerated Publication
Electrical characteristics of a vertically integrated field-effect transistor using non-intentionally doped Si nanowires

https://doi.org/10.1016/j.mee.2011.07.009Get rights and content

Abstract

In this paper, we report the fabrication and the electrical characterization of Vertical Gate All Around Field-Effect Transistors (GAA-FET) using nonintentionally doped Silicon NanoWires (SiNWs) grown by Chemical Vapour Deposition (CVD) using the Vapour–Liquid–Solid (VLS) mechanism as conduction channel. The SiNWs GAA-FET devices exhibited n-channel type semiconductor behaviour whereas the as-grown SiNW FET present p-type behaviour. This effect may be due to positive fixed charge located in the oxide shell or at the Si/SiO2 interface. Moreover we show that the threshold voltage at room temperature is around −0.95 V, a high ION/IOFF ratio up to 106 with a low IOFF current about 1 pA, a maximum transconductance (gm,max  0.9 μS at VGS = −0.65 V and VDS = 1 V) and a minimum inverse subthreshold slope around 145 mV/decade. In light of these characteristics, these devices can be suitable for high performance, low power consumption components and especially for high density integration in integrated circuits (ICs) interconnections regarding to their 3D architecture.

Introduction

Bottom-up approach has opened a new route for building blocks of future device applications such as field effect transistors, laser diodes, photovoltaic devices [1], [2]. The properties of nanowires have been widely studied mainly in planar configuration [3], [4] but recently it has been demonstrated that it is possible to use them as the conduction channel of vertical FET with the bulk-nanowire epitaxial interface as a source or drain contact. Different materials have been investigated such as ZnO [5], InAs [6], [7], [8], [9], and Si [10], [11], [12], [13]. One benefit of vertical integration is the possibility to build a wrapping gate with a cylindrical geometry which enhances the electrostatic gate coupling and improves the control of the gate potential in the wire body compared with planar devices. This configuration allows to build high performance and low power FET combined with a 3D integration providing a very promising way to increase the integration density on microelectronic circuits. Indeed the vertical integration offers a new option to integrate much more devices than in planar approach for the same surface area which is one of the main streams of microelectronics technology [14].

In this paper we report the fabrication and the electrical performance of a non-intentionally doped vertical SiNWs GAA FET using a generic process, which is also described. This process requires noncritical lithographic steps and allows the interconnection of several nanowires at the same time. Electrical performances are discussed and technological improvements are proposed in order to obtain better devices characteristics.

Section snippets

Experimental

The starting material for NW growth was 〈1 1 1〉-oriented n-type Si wafers (1  cm). In order to open windows for the localized deposition of NW catalyst, a photoresist layer was spun onto the substrate and patterned using photolithography, resist wastes were cleaned with oxygen plasma at 450 W for 60 s and native oxide was removed by dipping into HF (10%) for 10 s. Gold colloids acting as catalysts for the VLS growth were then deposited onto the patterned substrates by drop casting a droplet of

Discussion

Typical output characteristic of a SiNWs GAA FET device is displayed in Fig. 2b. The mean diameter of the oxidized wires is about 115 nm. The FET has n-type behaviour as verified from the current increase when we increase the gate voltage bias (Fig. 2a). We show that the subthreshold slope, which is a key parameter for low power switching applications, is around 145 mV/decade which is good but still more than twice the theoretical room temperature limit of 60 mV/decade. Indeed the subthreshold

Conclusion

In summary we have shown that it is possible to build vertical SiNWs based GAA-FET with good electrical characteristics such as a low subthreshold slope of 145 mV/decade, a high ION/IOFF ratio up to 106 which is the highest value reported for VLS grown undoped silicon nanowires vertical FET. Despite the fact this ratio is remarkably good it is still possible to improve it by playing on the contacts quality in order to obtain a better carriers’ injection in the channel. Our devices exhibited low

Acknowledgements

The authors thank the members of the technical staff of the PTA facilities at Grenoble (France) for their technical support. A part of this work was supported by the European Community’s Seventh Framework Programme (FP7/2007–2013) under grant agreement NANOFUNCTION n°257375.

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