A review of III-V Tunnel Field Effect Transistors for future ultra low power digital/analog applications

Abstract

Tunnel Field Effect Transistors (TFETs) have emerged as serious contenders for the replacement of traditional MOSFET technology for the future ultra low power Analog/Digital circuit applications because of their unique properties such as Sub-60 mV/decade subthreshold swing (SS), negligible short channel effects (SCEs) and very low off current (I_OFF). This review article intensively studies the RF/Analog and DC performance of III-V materials based TFETs. This article highlights the scalability of III-V TFETs, influence of thickness and permittivity of gate dielectric, interface trap density, other geometrical dimensions, material properties and various TFET architectures on the ON and OFF state performance of III-V TFETs. This paper also point outs the impact of temperature, strain, gate metal work function, source-gate overlap and underlap, doping concentration and supply voltage scaling on the DC, RF/Analog characteristics of III-V TFETs.

Introduction

At deep nanometer scale regimes, subthreshold leakage current severely degrades the DC and RF properties of transistors [[1], [2], [3], [4], [5], [6], [7], [8], [9], [10], [11], [12], [13], [14]]. Beyond 22 nm technology node, the power consumption has been a critical issue in the scaling of traditional silicon based CMOS technology [[9], [10], [11], [12], [13], [14], [15], [16], [17], [18], [19], [20], [21]]. Therefore, the researchers from all over the world have been working on TFET, I-MOSFET (Impact ionization-MOSFET), NEMFET (Nano-Electro-Mechanical FET) and NCFET (Negative Capacitance FET) technologies for the replacement of traditional MOSFETs in future ultra low power digital and analog circuit applications [[22], [23], [24], [25]]. TFETs, I-MOSFETs, NEMFETs and NCFETs can provide a SS of lower than 60 mV/dec which help them to achieve low power supply (V_DD) operation and low power dissipation. Poor reliability is the major limitation of I-MOSFETs. The use of a ferroelectric dielectric material under the gate of a TFET can effectively enhance the I_ON due to the formation of a negative capacitance (NC) effect. The TFETs with ferroelectric gate dielectric materials are known as NC-TFETs and they can outperform conventional TFETs. Poor on state current (I_ON), ambipolar current and degraded RF performance are the major limitations of conventional TFETs compared with MOSFETs of same dimensions [[26], [27], [28], [29], [30], [31], [32], [33], [34], [35], [36], [37], [38], [39], [40], [41], [42], [43], [44]]. However, this can be overcome by using channel-source interface engineering techniques like line tunnelling and heterojunction [26]. Line tunnelling TFETs are superior in performance compared with point tunnelling TFETs. TFETs have emerged as the most promising electronic switches due to their very low threshold voltages down to 0.2 V or lower at 300 K and high I_ON/I_OFF ratio [13]. The factors influences the threshold voltage (V_TH) of the TFETs fare work function of the gate metal used [37], effective channel length [12] and device geometry [44]. In order to obtain Sub-60 mV/dec SS in TFETs, the key requirement is a strong electrostatic-control of the channel by gate. The strong gate control of channel can be obtained by using nanowire structures or ultra thin body structures [27]. The ambipolar effects and poor I_ON of TFETs can also be improved by introducing strain in the channel layer [28]. Uniaxial compressive stress and biaxial tensile stress are found to be effective in improving the electrical characteristics of III-V nanowire TFETs [29,30].

III-V materials based TFETs can provide higher I_ON than conventional Silicon based TFETs [31]. The tunnelling efficiency of conventional Silicon TFETs are very low because the BTBT or zener tunnelling at channel-source tunnelling junction is based on the phonon-enabled indirect transition process. T shaped TFETs (TTFET) exhibited very low ambipolar current in comparison with vertical line TFETs [26]. The drain-gate overlap structure in TTFETs helps to minimize the ambipolarity effectively. Due to excellent saturation behaviour, TTFETs provides higher I_ON compared with L-shaped TFETs (LTFET) and vertical line TFETs. Reduced defect induced states in the bandgap and sharp band edges are the key requirements for TFETs in order to obtain Sub-60 mV/dec SS. In 2017, E. Memisevic et al. [32] studied the influence of band tails on the SS characteristics of III-V TFETs. SS of III-V TFETs can be expressed as [32].

$$SS=2.3\frac{kT{E}_0}{kT+E_0}\left(1+\frac{C_{it}}{C_{ox}}\right)$$

Where, E₀ is the energy decay parameter, k is a constant that models the concentration of states in the band, C_it represents the interface capacitance and C_ox represents oxide capacitance of the TFETs. III-V materials with smaller bandgaps degrade the I_OFF and SS characteristics of the TFETs [45]. Effective tunnelling mass of charge carriers and bandgap energy of source materials mainly determines the I_ON and I_OFF of TFETs [33,38]. III-V materials offer significantly low effective tunnelling mass compared with traditional silicon and germanium materials. Therefore, III-V TFETs can provide superior DC, analog and RF performance compared with silicon or germanium or SiGe based TFETs. The smaller effective carrier mass leads to the enhancement of tunnelling probability of carriers. The enhancement in BTBT rate due to lower effective carrier mass can significantly improve the transconductance (g_m), drain current, f_T (Cut-off frequency), f_max (Maximum oscillation frequency) and intrinsic gain which are the prime factors that determines the DC, analog and RF performance of TFETs. A semiconductor material with narrow bandgap provides higher I_ON but suffer from ambipolarity due to GIDL (Gate Induced Drain Leakage) [33,46]. On the other hand, a semiconductor with wider bandgaps improves the ambipolarity but suffer from poor I_ON in TFETs [33,46]. This paper investigates the various factors that affect the DC, RF and analog characteristics of III-V TFETs.