Design and performance of the ABCD3TA ASIC for readout of silicon strip detectors in the ATLAS semiconductor tracker

Abstract

The ABCD3TA is a 128-channel ASIC with binary architecture for the readout of silicon strip particle detectors in the Semiconductor Tracker of the ATLAS experiment at the Large Hadron Collider (LHC). The chip comprises fast front-end and amplitude discriminator circuits using bipolar devices, a binary pipeline for first level trigger latency, a second level derandomising buffer and data compression circuitry based on CMOS devices. It has been designed and fabricated in a BiCMOS radiation resistant process. Extensive testing of the ABCD3TA chips assembled into detector modules show that the design meets the specifications and maintains the required performance after irradiation up to a total ionising dose of 10 Mrad and a 1-MeV neutron equivalent fluence of 2×10¹⁴ n/cm², corresponding to 10 years of operation of the LHC at its design luminosity. Wafer screening and quality assurance procedures have been developed and implemented in large volume production to ensure that the chips assembled into modules meet the rigorous acceptance criteria.

Introduction

The Semiconductor Tracker (SCT) together with the Pixel Detector and the Transition Radiation Tracker (TRT) form the Inner Detector (ID) system in the ATLAS experiment being built for the Large Hadron Collider (LHC) at the CERN laboratory [1]. The SCT is built of double-sided modules, each one consisting of two pairs of daisy chained silicon strip sensors. The strips on the two sides are tilted by a small stereo angle of 40 Mrad, which provides the third space coordinate with a moderate resolution, i.e. z in the barrel part and r in the endcap parts. In the barrel part the strips are 12.8-cm long with a constant pitch of 80 μm. In the endcap discs of the SCT there are five different designs of the silicon strip sensor used. The electrical parameters of the barrel and the endcap sensors are very similar and the same front-end electronics can be used for the sensor of each type.

Each module comprises 1536 strips to be read out by means of 12 128-channel front-end ASICs, which are assembled into a hybrid circuit and attached to the sensor assembly. The complete SCT detector will consist of 4088 silicon strip detector modules comprising approximately 6.3 million readout channels.

There are two aspects that influence strongly the design of all components of the SCT, and of the front-end ASIC in particular, namely the bunch crossing frequency in the LHC of 40 MHz and the required radiation resistance. The design specifications for the SCT front-end electronics, assuming 10-year operation of the LHC at the design luminosity scenario, are: 10 Mrad of total ionising dose and 2×10¹⁴ n/cm² of 1-MeV neutron equivalent fluence, including 50% uncertainty. The front-end ASIC must maintain the specified performance parameters after irradiation up to the above total ionising dose and 1-MeV equivalent fluence. In order to meet these requirements a special radiation hard integrated circuit technology has to be used.

The moderate spatial resolution requirement of the SCT can be achieved with strip pitch of 80 μm and binary readout architecture that guarantees resolution of 23 μm rms. The main advantage of the binary readout system is a drastic reduction of data to be read out as only addresses of channels that have recorded hits above the threshold are transmitted off the detector. For a big tracking system like the SCT this is an important aspect resulting in lower cost, a reduction of the material required for the data transmission system, and simplified off-detector readout electronics. On the other hand, in order to perform data sparsification in the front-end electronics a very robust front-end readout system is required. Besides the usual requirements concerning noise, speed and power dissipation, the channel-to-channel matching of gain, and discriminator threshold become very critical issues.

Another aspect, particularly important for the binary readout architecture, is the immunity of the overall system, and so of each component of the system, to external and internal interference, usually referred to as common mode noise. If one takes into account irreducible noise sources present in the front-end system, i.e. the parallel and series noise sources of the preamplifier and the shot noise of the detector leakage current, an achievable signal-to-noise ratio is about 15 at the beginning of the experiment and about 10 after irradiation of silicon strip detectors and front-end electronics up to the levels as expected after 10 years of LHC operation. With these signal-to-noise ratios there is very little room for setting the discrimination threshold in such a way that the detector is fully efficient and the noise occupancy is much lower than the physical data rate. Thus, any degradation of the signal-to-noise ratio will lead to either a drastic reduction of efficiency or increase of noise occupancy.

The ABCD3TA design is a single chip implementation of the binary readout architecture using the DMILL technology—a radiation resistant BiCMOS process comprising CMOS devices with 0.8 μm minimum gate length and bipolar devices with the cut-off frequency of 5 GHz. The final design is an outcome of several prototyping steps. The actual implementation of the required architecture and functionality depends strongly on the available technological options. At the beginning of the project a version based on two separate chips: CAFE [2]—a front-end chip realised in the MAXIM bipolar process and ABC [3]—a binary pipeline chip realised in the Honeywell bulk CMOS process, have been developed. The DMILL process [4], which became available at a later stage, permits combining all required functionality in a single chip. The ABCD3TA design follows closely the first prototype developed in the DMILL process, the SCT128B chip [5].

The first ABCD prototype chip met most of the requirements, however, the spread of the discriminator threshold in the front-end exceeded the acceptable level. Analysis of the problem led us to a conclusion that given the matching parameters of the DMILL technology we could not achieve the required performance following the original circuit concept. Therefore, the design was upgraded and in the ABCD2T chip threshold correction on a channel basis was implemented by adding a 4-bit digital-to-analogue converter (TrimDAC) per channel [6], [7]. Extensive radiation testing performed for that prototype showed that matching performance degraded significantly after irradiation. In particular, after proton irradiation up to the full fluence the discriminator offset spread exceeded the range of the TrimDAC. Therefore, in the final version ABCD3TA the TrimDAC range adjustment was added to ensure that the offset spread is covered even in the case of a very large increase after irradiation, up to a factor of 5.