Elsevier

Solid-State Electronics

Volume 164, February 2020, 107701
Solid-State Electronics

Surface Ge-rich p-type SiGe channel tunnel field-effect transistor fabricated by local condensation technique

https://doi.org/10.1016/j.sse.2019.107701Get rights and content

Highlights

  • Tunnel field-effect transistor (TFET) which has surface Ge-rich SiGe nanowire as a channel has been demonstrated.

  • Use a technique called Ge condensation to increase surface Ge content.

  • The experiment results showed that the performance of the p-channel TFET device was improved.

Abstract

In this study, tunnel field-effect transistor (TFET) which has surface Ge-rich SiGe nanowire as a channel has been demonstrated. There are improvements in terms of on-current and subthreshold swing (SS) comparing with control groups (constant Ge concentration SiGe TFET and Si TFET) fabricated by the same process flow except for the channel formation step. In order to obtain the concentration-graded SiGe channel, Ge condensation method which is a kind of oxidation is adopted. The rectangular shape of the channel becomes a rounded nanowire through the Ge condensation process. The TFET with the concentration-graded SiGe channel can improve drive current due to a smaller band gap at the Ge-condensed surface of the channel compared to Si or non-condensed SiGe channel TFET.

Introduction

Tunnel field effect transistors (TFETs) have been regarded as promising energy efficient switching devices because they can achieve subthreshold swing (SS) below 60 mV/decade, which is the limit of conventional metal-oxidesemiconductor FETs (MOSFETs) at the room temperature. [1]. Carrier injection mechanism in TFETs relies on band-to-band tunneling (BTBT) less affected by temperature. At small gate voltages (VGS), the Fermi-tail part is cut from participating in the current drive, resulting in a small off current and SS [2], [3]. It has been reported that tunneling rate of carriers from source to channel is inversely proportional to the band gap of channel materials [4]. Therefore, materials having a small band gap are preferred to increase the current of TFET. In recent years, extensive research has been conducted to improve on-current. Various materials have been studied to reduce the width and height of tunnel barriers [5], [6], [7]. That is, using Ge or SiGe rather than Si may be a good alternative to reduce the tunneling barrier. In addition, SiGe is complementary MOS (CMOS) compatible because it is a group IV material [8]. Also, Ge or SiGe have high hole mobility and might be promising for pTFETs [9], [10], [11], [12], [13], [14]. Although high Ge content is preferred for improving the on-current, there is a trade-off especially in terms of process capability due to the crystal lattice mismatch with the Si substrate which increases the defect concentration on the channel surface. Fig. 1 shows dislocation lines starting from interface between Si substrate and SiGe channel. These lines act as trap sites on the surface and degrade the mobility of carriers when current flows through the SiGe channel.

This paper aims to solve the abovementioned problems. we fabricate p-channel SiGe nanowire with graded Ge concentration. The proposed SiGe channel has high Ge concentration (about 45%) at the channel surface to boost on-current, while Ge content is low (about 20%) at the interface between SiGe and Si substrate to reduce the lattice mismatch. In order to verify the feasibility, technology computer-aided design (TCAD) simulation are preceded. As the control groups, SiGe channel TFET with constant Ge content of 20% and Si channel TFET are fabricated. By changing channel Ge concentration, improvements of electrical characteristics are observed. In addition, in order to improve gate controllability in the SS region, post metallization annealing (PMA) with high pressure condition is performed to reduce the interface trap density.

Section snippets

Device structure

Fig. 2(a) and (b) depict a schematic of the fabricated device and process flow, respectively. In this study, three different structures are fabricated. The step that makes the difference between the experimental group and the control group is the active formation step. After active Si fin etch, Si TFET without SiGe epitaxial growth step are made into a control group. After SiGe epitaxial growth, the group in which the Ge condensation step is omitted is made into the other control group (Si0.8Ge

Experiment

The actual experiments are performed in the order shown in Fig. 2(a), and unit tests are conducted for some important steps such as active formation step and Ge condensation step. Devices are fabricated on the full 6 in sized Si-on-insulator (SOI) substrate. Si dioxide (SiO2) used as buried oxide layer has 375 nm thickness while silicon as a substrate is 60 nm thickness. The process of forming the active channel at the front-end-of-line (FEOL) is very important, and a related figure is shown in

Result and discussion

The cross-section of the channel after two step oxidations (rounding oxidation & Ge condensation) is shown in Fig. 2(d). By energy-dispersive x-ray spectroscopy (EDS), of Fig. 5 shows that the initial Ge content is about 20% and the Ge content of the channel surface reaches to ~45% after Ge condensation. The core part (bright part in the figure) is pure Si, but it can be seen that the portion surrounding the core (dark part of the figure) is SiGe and the Ge content increases to ~45% with

Conclusions

In this study, the TFET with Ge-condensed SiGe nanowire channel is demonstrated. The problem of directly growing SiGe with a high concentration of Ge on a Si substrate is solved by using a technique called Ge condensation with SiGe initially having low concentration of Ge (~20%). We have confirmed that the ION and SS are improved as expected from the TCAD simulation. The omega shaped nanowires are formed by the two step oxidation processes; The first oxidation is the edge-rounding oxidation of

Declaration of Competing Interest

The authors declare that they have no known competing financial interests or personal relationships that could have appeared to influence the work reported in this paper.

Acknowledgments

This work was supported in part by the Brain Korea 21 Project in 2019, in part by the Future Semiconductor Device Technology Development Program (10067739 & 10080575) funded by Ministry of Trade, Industry and Energy (MOTIE) and Korea Semiconductor Research Consortium (KSRC), and in part by Synopsys Inc.

Junil Lee was born in Changwon, Korea, in 1987. He received the B.S degree in Electrical Engineering from Seoul National University in 2013. He is currently working toward Ph.D degree in electrical engineering. His research interests include nanoscale devices, tunnel field-effect transistor (TFET). Mr. Lee is a Student Member of the Institute of Electrical and Electronics Engineers (IEEE) and the Institute of Electronics Engineers of Korea (IEEK).

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Junil Lee was born in Changwon, Korea, in 1987. He received the B.S degree in Electrical Engineering from Seoul National University in 2013. He is currently working toward Ph.D degree in electrical engineering. His research interests include nanoscale devices, tunnel field-effect transistor (TFET). Mr. Lee is a Student Member of the Institute of Electrical and Electronics Engineers (IEEE) and the Institute of Electronics Engineers of Korea (IEEK).

Byung-Gook Park received his B.S. and M.S. degrees in electronics engineering from Seoul National University (SNU) in 1982 and 1984, respectively, and his Ph. D. degree in electrical engineering from Stanford University in 1990. From 1990 to 1993, he worked at the AT&T Bell Laboratories, where he contributed to the development of 0.1 micron CMOS and its characterization. From 1993 to 1994, he was with Texas Instruments, developing 0.25 micron CMOS. In 1994, he joined SNU as an assistant professor in the School of Electrical Engineering (SoEE), where he is currently a professor. In 2002, he worked at Stanford University as a visiting professor, on his sabbatical leave from SNU. He led the Inter-university Semiconductor Research Center (ISRC) at SNU as the director from 2008 to 2010. His current research interests include the design and fabrication of nanoscale CMOS, flash memories, silicon quantum devices and organic thin film transistors. He has authored and co-authored over 1000 research papers in journals and conferences. Prof. Park has served as a committee member on several international conferences including Microprocesses and Nanotechnology, IEEE International Electron Devices. Meeting, International Conference on Solid State Devices and Materials, and IEEE SiliconNanoelectronics Workshop and served as an Editor of IEEE Electron Device Letters. He received “Best Teacher” Award from SoEE in 1997, Doyeon Award for Creative Research from ISRC in 2003, Haedong Parper Award from the Institude of Electronic Engineers of Korea (IEEK) in 2015, Educational Award from College of Engineering, SNU, in 2006, Haedong Research Award from IEEK in 2008, Nano Research Innovation Award from the Ministry of Science, ICT and Future Planning of Korea in 2013, and Academic Training Award from Seoul National University in 2015.

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