Highly selective etch process for silicon-on-insulator nano-devices

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Abstract

Reactive ion etch (RIE) processes with HBr/O2 chemistry are optimized for processing of functional nanostructures based on silicon and polysilicon. The etch rate, etch selectivity, anisotropy and sidewall roughness are investigated for specific applications. The potential of this process technology for nanoscale functional devices is demonstrated by MOSFETs with 12 nm gate length and optimized photonic devices with ultrahigh Q-factors.

Introduction

The International Technology Roadmap for Semiconductors (ITRS) predicts the necessity of novel, non-planar metal-oxide-semiconductor field effect transistors (MOSFETs) to fulfill its stringent scaling guidelines [1]. Candidates for such three-dimensional devices are transistors with multiple gates such as FinFETs or Triple-Gate MOSFETs, usually fabricated on silicon-on-insulator (SOI) substrates [2], [3], [4], [5]. SOI technology for multi-gate CMOS, however, results in a three-dimensional topography and therefore imposes new challenges for reactive ion etch (RIE) processes. In detail, an extremely high etch selectivity of polysilicon gates over thin gate oxides has to be achieved while maintaining anisotropic profiles [6], [7], [8], [9].

In addition, SOI material enables high integration density for photonic devices due to the large contrast in refractive index of silicon and silicon dioxide (SiO2). For low-loss SOI photonic solutions, it is critical to optimize manufacturing tolerances and especially to minimize surface roughness of etched sidewalls [10].

In the first part of this work an inductively coupled plasma reactive ion etch (ICP-RIE) process is described, which meets the requirements concerning high etch selectivity, anisotropy and smooth surface morphology for device fabrication on SOI substrates. In the second part two applications are described. First, electrical characteristics of 12 nm electrical junction (EJ-MOSFETs) are presented. These devices are excellent test structures to prove the limits of scalability down to the deca-nanometer regime [11], [12]. Second, high quality microring resonators are shown to demonstrate the low losses of optical wave guides fabricated with the developed etch technology.

Section snippets

Experimental

An etch process for structuring silicon and polysilicon with dimensions down to the deca-nanometer regime has been developed using an Oxford Instruments Plasmalab System 100 ICP-RIE tool. The ICP source is supplied with RF power at 2 MHz from a 5 kW generator. An aluminum lower electrode is independently biased with 13.56 MHz RF power from a generator with a maximum power of 600 W. The sample temperature has been maintained at 10 °C during etching using backside helium cooling. All experiments have

EJ-MOSFET

EJ-MOSFETs, as shown in Fig. 3, are double gate devices with an additional gate electrode placed over the conventional switching gate. This additional gate electrode, usually labeled as upper gate, induces inversion layers at the silicon/gate oxide interface, which connect the doped source/drain regions to the inner transistor. EJ-MOSFETs are thus ideal test devices to explore the limits of transistor scaling, because doping gradient related short channel effects are eliminated. The lower gate (

Conclusion

A reactive ion etch process for silicon and polysilicon using HBr/O2 plasma chemistries has been investigated. A highly selective yet anisotropic process resulting in smooth etched sidewalls has been demonstrated. It has been applied to yield fully functional Triple-Gate EJ-MOSFETs on SOI with a gate length of 12 nm. Furthermore, sidewall roughness has been proven to be negligible by fabrication and characterization of silicon microring resonators on SOI with a ultrahigh Q-factor of 139.000.

Acknowledgments

The authors thank B. Hadam for SEM imaging and N. Delchev for careful sample preparation. This work has been partly supported by the German Bundesministerium für Bildung und Forschung (bmb+f) under contract number 01 M 3101 (“HSOI”) and 13 N 7805 (“Extended CMOS”) and by European Commission under contract no. IST-2001-38919 (PHOENIX) and the Ministerium für Wissenschaft und Forschung des Landes Nordrhein Westfalen.

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Present address: Institut für Angewandte Physik, Universität Tübingen, Auf der Morgenstelle 10, 72076 Tübingen, Germany.

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