Nickel-silicide process for ultra-thin-body SOI-MOSFETs
Introduction
Scaling of CMOS transistors has reached a point, where new materials and new architectures are needed to fulfil the requirements set by the International Technology Roadmap for Semiconductors (ITRS) [1]. Silicon on insulator (SOI) is a promising material for future nanoscale CMOS circuits, especially if the thickness of the top-silicon or device layer is scaled far below 100 nm. Devices manufactured on such ultra-thin SOI are fully depleted in the off-state and exhibit superior short channel behaviour compared to bulk silicon or even partially depleted, thick SOI [2].
A major concern with ultra-thin-body (UTB) SOI MOSFETs is a large parasitic source to drain resistance due to extremely thin top-silicon films (see schematic in Fig. 1(a)), which severely limits device on-currents and performance. Promising solutions to reduce the resistivity are raised source and drain areas manufactured by selective epitaxy [3], by self-aligned polysilicon [4] or by self-aligned silicidation [5].
Nickel silicide has excellent electrical properties and has been investigated for reduction of source/drain resistivity [6] and as gate electrodes for next generation nano-CMOS devices [7]. In this work, a self-aligned nickel silicide process for source and drain leads of UTB MOSFETs on SOI is studied. Electrical parameters such as on-currents, source/drain resistivity and front and back interface trap densities are discussed for different devices with top-silicon thicknesses down to 15 nm.
Section snippets
Device fabrication
UTB MOSFETs have been fabricated using SOI-material with a buried oxide thickness (BOX) of tBOX = 200 nm and a top-silicon film in 〈1 0 0〉 orientation of tSi = 100 nm. The channel has been implanted with a Boron dose of 7E + 12 ions/cm2 at 18 keV, followed by a rapid thermal anneal (RTA) at 1100 °C for 4 min in inert ambient. The top-silicon layers have been thinned down to 80, 60, 30 and 15 nm, respectively, using dry oxidation and subsequent HF wet etch. The top-silicon etching for source, channel and drain
Experimental results and discussion
All measured transistors have gate lengths of L = 2 μm and gate widths of W = 20 μm. Output and transfer characteristics have been measured before and after nickel silicidation using an Agilent Parameter Analyser (4156B). Fig. 3(a) shows typical output characteristics – drain current IDS against source/drain voltage VDS – of an n-MOSFET on 15 nm top-silicon without nickel silicidation. The output characteristics after silicidation are shown in Fig. 3(b). In both cases, the drain/source-current is
Conclusions
In this work, a self-aligned nickel silicide process for ultra-thin-body SOI-MOSFETs has been successfully demonstrated. An increase of transistor on-currents Ion with a factor of up to 100 after silicidation has been observed. This gain is much more pronounced if the top-silicon thickness is decreased and this is attributed to dopant fluctuations in non-silicided source/drain leads in UTB MOSFETs with tSi = 15 nm. Even though it has been shown that the BOX/top-silicon interface has a comparable
Acknowledgements
Financial support by the Bundesministerium für Bildung und Forschung (bmb+f) under contract number 01 M 3142 A “KrisMOS” and by the European Commission under the frame of the Network of Excellence “SINANO” is gratefully acknowledged.
References (11)
- et al.
Towards implementation of a nickel silicide process for CMOS technologies
Microelectron. Eng.
(2003) - et al.
Highly selective etch process for silicon-on insulator nano-devices
Microelectron. Eng.
(2005) - International Technology Roadmap for Semiconductors: 2002 Update, International Sematech. Available from:...
- et al.
ULSI Devices
(2000) - et al.
A 50 nm depleted-substrate CMOS transistor (DST)
IEDM Tech. Dig.
(2001)