Elsevier

Microelectronic Engineering

Volume 110, October 2013, Pages 224-228
Microelectronic Engineering

Definition of 15 nm half pitch grating structures by electron beam lithography double exposure techniques

https://doi.org/10.1016/j.mee.2013.04.013Get rights and content

Highlights

  • 15 nm half pitch resist structures in 40 nm HSQ resist.

  • Using standard processing, without salty development or development at high temperatures.

  • Realized using double exposure technique.

  • Alignment accuracy between subsequent exposures better than 5 nm.

Abstract

In this work a novel technique for the definition of 15 nm half pitch line/space grating structures by means of an electron beam double exposure approach using a Vistec EBPG 5200 e-beam tool is presented. The 1:1 line/space ratio grating is defined in two subsequent lithographic process cycles in which two 1:3 line/space grating shifted by twice the line width are exposed. This allows the definition of such dense 15 nm half pitch gratings without the need of using salty development, hence in a CMOS compatible fashion.

The main challenge of this approach, the overlay accuracy between the two subsequent exposures, is addressed by a sophisticated strategy regarding the fabrication of the markers used to align both exposures. Using this strategy overlay accuracy better than 5 nm has been achieved for the majority of the fabricated structures.

Introduction

The ITRS Roadmap calls for the lithographic definition of structures with a half pitch of ∼15 nm for several fields of application, including Flash, DRAM and MPU/Logic, within the next 3–6 years [1]. Similar structures can also be used as basic building blocks in other field of applications such as nanosensing. Several approaches have recently been presented which allow the definition of such dense structures in hydrogen silsesquioxane (HSQ) by means of electron beam lithography (EBL) [2], [3]. Most of those approaches are based on the use of salty developer solutions, which improve the contrast of the development process and hence the resolution. As a downside, the use of salty developers is not compatible with standard CMOS processing and leads to an increase in line edge roughness (LER) and line width roughness (LWR) of the resist features. Therefore, those approaches, while fulfilling the ITRS half pitch resolution requirements, fail to meet other important criteria such as compatibility with standard processing guidelines and ITRS target values for LER and LWR.

In addition to the development process proximity effects (PE) are limiting factors for the resolution of dense structures defined by EBL. Conventionally, a PE correction (PEC) is applied to compensate the detrimental influence of the PE on resolution. Unfortunately, the benefits of a PEC for such dense nanostructures are very limited. Neither a PEC based on a dose correction nor a PEC based on modifying the shape of the exposed figures is able to fully compensate the PE in this regime.

Using a conventional exposure strategy to realize dense nanostructures with sub-20 nm feature sizes the PE limits the achievable resolution (mainly by means of forward scattering and beam blur). In Fig. 1 the effective exposure intensity of a 15 nm half pitch grating structure with a line/space ratio of 1:1 obtained in simulation is plotted as red line. Lines, exposed with a constant dose, and spaces are shown as black and white bars on top the plot, respectively and as a guide to the eye the outlines of desired line profiles are plotted as dashed lines. From this plot can be seen that the intensity modulation, and hence the dose difference, between the exposed lines and the unexposed spaces separating the lines is quite low due to the PE. At no point in the profile the effective dose comes close to a value which could be interpreted as unexposed. Even with a high contrast development process such features cannot be resolved during development. Hence, to enable the fabrication of such dense nanostructures using conventional CMOS compatible processing other approaches have to be found.

In this work a novel fabrication process is presented which limits the influence of the PE and other effects on pattern resolution without applying a conventional PEC. This fabrication process is based on the following idea: The exposure of a dense grating structure is divided into two separate subsequent exposures of less dense structures in such a way that both partial exposures do not influence each other via PE, hence significantly reducing the overall influence of the PE on the achievable resolution. A similar approach has been shown in Ref. [4], yielding 15 nm half pitch structures. Fig. 2 shows a plot of the simulated effective exposure intensity of a 15 nm line/space structure with a line/space ration of 1:3. It can be clearly seen that, compared to Fig. 1, the intensity modulation is significantly enhanced. This leads to a better dose contrast between exposed and unexposed regions of the design, allowing to resolve such structures using a CMOS compatible development process with sufficiently high contrast.

Section snippets

Experimental

Standard silicon substrates have been used for all experiments. In a first fabrication step, markers have been defined by means of electron beam lithography using a Vistec EBPG 5200 tool operated at 100 kV. The markers have then been transferred into the substrate using reactive ion etching. To achieve the desired overlay accuracy of well below 10 nm special care has been taken to ensure that each marker could be exposed in the center of a main field, hence without a significant beam deflection,

Results and discussion

One key issue for the successful implementation of this fabrication scheme is the precise control of the overlay between both partial exposures. Even a slight misalignment of only a few nanometers is clearly visible on this scale, as can be seen from the SEM micrograph shown in Fig. 4. Therefore, as described above, special care has been taken to improve the overlay accuracy, including the adoption of a sophisticated exposure strategy for the marker layer. In general, we observed an overlay

Conclusion

Using the double exposure approach presented in this work we have fabricated 20 nm and 15 nm half pitch line/space gratings with reasonably low LER and LWR in a CMOS compatible fashion. Using a sophisticated exposure strategy for the definition of the markers used to align the two subsequent exposures two each other we observed an overlay accuracy which was in general well below 10 nm and in almost all cases well below 5 nm which is significantly below the specification of the Vistec EBPG 5200 tool

Acknowledgement

The authors wish to thank B. Chmielak, Institute of Semiconductor Electronics, Aachen University, for the SEM inspection of the fabricated samples. The authors also acknowledge financial support by the DFG project “Experimentelle und theoretische Untersuchung der Wirkungsweise von Silizium-Nanodraht-MOSFETs” as well as funding from the European Community’s Seventh Framework Program (FP7/2007-2013) under grant agreement NANOFUNCTION n 257375.

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