Elsevier

Microelectronic Engineering

Volume 178, 25 June 2017, Pages 245-249
Microelectronic Engineering

Research paper
Ultra-low power 1T-DRAM in FDSOI technology

https://doi.org/10.1016/j.mee.2017.05.047Get rights and content

Abstract

A systematic study of a capacitorless 1T-DRAM fabricated in 28 nm FDSOI technology is presented. The operation mechanism is based on band modulation. The Z2-FET memory cell features a large current sense margin and small OFF-state current at 25 °C and 85 °C. Moreover, low power consumption during state ‘1’ writing is achieved with ~ 0.5 V programming voltage. These specifications make the Z2-FET an outstanding candidate for low-power eDRAM applications.

Introduction

Dynamic Random Access Memory or DRAM is a prominent product of semiconductor industry. The scaling of the embedded capacitor makes the future development of conventional DRAM cells very challenging. To overcome this issue, the concept of capacitorless DRAM in SOI technology was proposed. It utilizes the floating-body of a MOS transistor to store the information instead of the external capacitor. These devices are known as single-transistor capacitorless 1T-DRAM memories [1], [2], [3], [4], [5].

The simple fabrication, the release of supercoupling effect thanks to its ultra-thin body [6], [7], the long retention time [8] and the large read current promote the Z2-FET as the favorite candidate among several 1T-DRAM variants [9], [10], [11], [12], [13], [14]. We investigate the physical mechanisms and the performance of this memory cell implemented in the 28 nm FDSOI technology node [15]. We demonstrate that the device operation relies mainly on the effective carrier lifetime [16] that is controlled by the ultrathin film and interfaces.

Section 2 describes the structure of the device and its characteristics. The memory operation is investigated experimentally in Section 3 and validated by TCAD simulations [17] in Section 4. The current margin dependence on temperature is presented in the final section.

Section snippets

Device structure and operation principle

The Z2-FET (Fig. 1) is a forward biased, partially gated, P-I-N diode with an undoped ultrathin silicon film (tsi = 7 nm). The cathode (N+ doped source) is grounded and the anode (P+ doped drain) is positively biased. In 28 nm FDSOI [15] technology, the Z2-FET is fabricated with a thin buried oxide (tBOX = 25 nm) and a raised epitaxial layer (tepi = 15 nm) in the drain, source and ungated regions to reduce the series resistance [18]. The front-gate (VGF) and back-gate (ground-plane, VGB) are biased to

Z2-FET as 1T-DRAM memory

The memory measurements were performed using Agilent B1530A unit with two channels to pulse VA and VGF. The cathode was kept grounded and the back gate was negatively biased with a constant voltage (VGB =  1 V).

To program the memory state ‘1’, electrons are stored under the front gate. For ‘0’ state, the area underneath the gate is depleted of electrons. The states are being read with a VA pulse expected to discharge the electrons available under the front gate [12].

The bias pattern for memory

TCAD simulations

The Z2-FET memory operation is analyzed via 2D Synopsys TCAD simulations. Fig. 4 shows the hold-write-hold-read pattern applied on the device. The experimental results are confirmed by the simulated current window (I1-I0) which is equal to 23 μA/μm.

At ‘0’ programming state, the hole density remains high in gated part of the channel which operates in deep depletion mode. Similarly, the electrons concentration is high in the ungated region and also causes deep depletion. Hence, the electron/hole

Current sense margin dependency on temperature

The continuous reading of logic ‘0’ (without holding stage) consists first of programming ‘0’ state and then applying a long VA signal for > 550 ms. Fig. 6 shows the long retention time (tre > 500 ms) obtained even at high temperature for VA = 1.05 V and different front gate voltages. I0 at VGF = 1.3 V is relatively high but can easily be reduced to zero by raising VGF up by just 200 mV.

The sensing margins at room temperature and 85 °C are highlighted in Fig. 7. The reading currents I1 and I0 increase at

Conclusion

A capacitorless 1T-DRAM fabricated with 28 nm FDSOI technology has been demonstrated experimentally. The memory operation has been investigated via 2D simulations. Systematic and extensive measurements show that Z2-FET is able to deliver significant current margin with very low programming voltages. The OFF-state current is negligible and the memory operates in a wide temperature range. These attractive features make the Z2-FET device an ideal candidate for ultra-low power embedded memory

Acknowledgment

Financial support from the EU project REMINDER is appreciated.

References (22)

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    Scalability study on a capacitorless 1T-DRAM: from single-gate PD-SO1 to double-gate FinDRAM

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