P4-To-VHDL: Automatic generation of high-speed input and output network blocks
Introduction
Embedded hardware is nowadays used in almost every advanced technical system. Very typically, the embedded architecture contains more processing cores which need to communicate and exchange data. This communication can be inspired from the field of computer networks. Moreover, developers of NoC (Network on Chip) can reuse knowledge from this area which leads to faster development of final product. The number of computers and mobile devices is still rising which leads to higher bandwidth utilization. There is also a requirement to analyze all data in real time which is quite complicated to fulfil in pure software tools. Therefore, it is typical to embed the time-critical parts of networking operations into hardware accelerators. The advantage of this approach is the performance and native parallelism of hardware. However, development of networking hardware is quite complicated discipline and it isn’t easy to meet all required parameters like frequency, throughput or used resources. Very common are hardware accelerators with FPGA chips because such solutions are flexible and fast enough for processing of high-speed traffic even at speed of 100 Gbps.
From above description, we feel that it is quite complicated to find an expert who understands the FPGA technology and domain-specific problems (like computer network security, etc.). Therefore, high-level languages (HLL) seem to be suitable for such developers because they allow describing the hardware in simpler languages than VHDL or Verilog. Unfortunately, this level of abstraction suffers from performance penalty and there is a need to have a tool which is capable to meet a trade-off between the level of abstraction and reached performance.
P4: Programming Protocol-independent Packet Processors [1], [2] is novel and open source language which seems to be suitable for the description of modern network devices. It also evades the typical problem of classical network approaches, such as a fixed set of supported protocols, fixed set of actions, and so on. The main idea of this language is the capability to map a P4 program onto computational resources like FPGAs, graphics cards or programmable switches. We contribute towards the vision of P4 by designing and evaluating a generator of high-speed packet parser and deparser suitable for FPGAs. The generator’s output is a synthesizable VHDL code that performs packet parsing and deparsing as defined by the P4 program. Internal structure of both modules is inspired by hand-written modules which were developed by a skilled HDL programmer.
This paper introduces results of our continuing research which was initially published in [3], [4]. In this paper, we provide details of output network block (Deparser), the detailed description of Parser-Deparser approach and analysis of three use cases. The rest of the paper is organized as follows: Section 2 provides more details about the P4 language aspects that are relevant for this work. Section 3 introduces the basic ideas of Parser-Deparser approach and compares our work to conventional packet editor. Section 3.1 provides details about Parser’s architecture and transformation algorithm from P4 to VHDL. The section also provides a description of available optimizations. Section 3.2 provides details about Deparser’s architecture and transformation from P4 to VHDL. Section 4 provides results of our generator and compares them to a hand-written parser. The section also provides results for generated Deparsers which are supporting the same set of protocols. Section 5 presents other papers related to our work. Finally, Section 6 concludes the paper with important outcomes.
Section snippets
P4 Language
P4: Programming Protocol-independent Packet Processors [1], [2] is a high-level, platform-agnostic language. It represents a recent contribution to the broader idea of Software-Defined Networking (SDN) and its ecosystem. The main purpose of P4 is to provide a way to define packet processing functionality of network devices, paying attention to reconfigurability in the field, protocol independence and target (platform) independence. Using relatively simple syntax, P4 allows to define five basic
Device structure
The basic idea of the Parser-Deparser approach was introduced by Gibb in [5] and we adopted it into our approach. The generated device consists of three basic modules. The first module, Parser, is used to break the incoming network data into individual header fields. The output of this module is a set of extracted fields and corresponding valid bits. The valid bit is used for presence indication of extracted protocol fields in the currently processed packet. All extracted protocol fields and
Experimental results
In this section, we introduce the results for Parser and Deparser. We have tested properties of generated parsers with two different protocol stacks:
- •
full - Ethernet, 2 × VLAN, 2 × MPLS, IPv4/IPv6 (with 2 × IPv6 extension headers), TCP/UDP, ICMP/ICMPv6
- •
simple L2 - Ethernet, IPv4/IPv6 (with 2 × IPv6 extension headers), TCP/UDP, ICMP/ICMPv6
For each protocol stack, we compare the manually optimized HFE M2 Parser and the generated Parser with all optimizations enabled. The Deparser isn’t
Related work
In this section, we introduce a related work to both main modules - Parser and Deparser. We also introduce basic tools and available source code of the P4 community.
Conclusion
The paper presents the generator of two blocks - Parser and Deparser. The Parser block is important because each networking device needs to parse incoming data in order to perform subsequent actions like forwarding, measuring, packet editing, or any other general processing. The output block, Deparser, is used for packet assembling from parsed and possibly modified headers. This paper also introduces the Parser-Deparser approach which is an elegant and novel approach to general packet
Acknowledgment
This research has been supported by the “CESNET E-infrastructure” project no. LM2015042 funded by the Ministry of Education, Youth and Sports of the Czech Republic, the grant SGS15/122/OHK3/1T/18 funded by MEYS, by the European Union in the context of the BEBA project (Grant Agreement: 644122), the project Reg. No. CZ.02.1.01/0.0/0.0/16_013/0001797 co-funded by the MEYS and ERDF and the “NFV200” project TH02010214 funded by the Technology Agency of the Czech Republic.
Pavel Benáček works as a researcher at hardware department of Liberouter project which belongs to CESNET (Czech Educational and Scientific Network). He got his Ph.D. degree from Faculty of Information Technology CTU in Prague. He is focused on usage of high-level languages, development of novel architectures and algorithms for high-speed computer networks.
References (18)
- et al.
Netpdl: an extensible XML-based language for packet header description
Comput. Netw.
(2006) - et al.
P4: programming protocol-independent packet processors
SIGCOMM Comput. Commun. Rev.
(2014) - P4 Language Consortium, P4,...
- et al.
P4-to-VHDL: automatic generation of 100 Gbps Packet Parsers
2016 IEEE 24th Annual International Symposium on Field-Programmable Custom Computing Machines (FCCM), Washington D.C., USA
(2016) - et al.
Automatic generation of 100 Gbps packet parsers from P4 description
First International Workshop on Heterogeneous High-performance Reconfigurable Computing, Austin, TX, USA
(2015) Reconfigurable Hardware for Software-Defined Networks
(2013)- et al.
Low-latency modular packet header parser for FPGA
Proceedings of the Eighth ACM/IEEE Symposium on Architectures for Networking and Communications Systems
(2012) - P4 Language Consortium, P4-HLIR,...
- Liberouter, Netcope,...
Cited by (0)
Pavel Benáček works as a researcher at hardware department of Liberouter project which belongs to CESNET (Czech Educational and Scientific Network). He got his Ph.D. degree from Faculty of Information Technology CTU in Prague. He is focused on usage of high-level languages, development of novel architectures and algorithms for high-speed computer networks.
Viktor Puš got his Ph.D. degree from Faculty of Information Technology, Brno University of Technology in 2012.Viktor is a researcher with focus on hardware acceleration of timing-critical operations in the network,particularly in the network security monitoring.He is an author of one U.S. patent and many research papers published at renowned international conferences.
Hana Kubátová is a head of the Department of Digital Design at Faculty of Information Technology CTU in Prague.Her research interests are in the area of dependable (highly reliable, fault-tolerant and fail-safe) digital design methods for programmable hardware platforms, dependability modeling and dependability parameters computations, formal methods (Petri nets) in modeling, simulation and hardware design (automatic transformation from formal models to hardware implementations), logic synthesis and on-line testing methods. She is a member of a board of directors of EUROMICRO, a member of an editorial board of MICPRO journal and a program committee member of numerous conferences.
Tomáš Čejka is a Ph.D. candidate and an assistant professor at the Faculty of Information Technology, Czech Technical University in Prague. He also works as a researcher and developer in CESNET, the operator of the Czech NREN, in the Liberouter team. He is interested in network monitoring and network security in high-speed computer networks.