Studies of the quality of GdSiO–Si interface
Introduction
GdSiO has been found to exhibit a sufficiently high dielectric constant and band offset with respect to silicon to be considered as a potential high-k dielectric of the future [1], [2], [3]. Another advantage of this material is high thermal stability (demonstrated in the case of TiN gates), which is of extreme importance in the case of gate first approach [1], [2], [4].
High-k dielectrics, while offering reduced leakage current, suffer from numerous reliability issues associated with structural defects, mostly related to oxygen vacancies [5]. Due to bandgap widths lower than that of SiO2 charge trapping is more severe in these materials. The charge trapping phenomena in high-k dielectrics are more complex than in the case of SiO2 because of rather complicated stoichiometry [e.g. 2] and the presence of the interfacial layer. While numerous studies of the reliability of HfO2-based gate stacks under electrical stress have been reported [6], [7], [8], [9], [10], [11], [12], relatively few papers have been devoted to GdSiO. A detailed analysis of charge trapping in GdSiO has been described in [13], [14], but it was based on MIS capacitors and variation of interface trap density with stress was not considered.
The goal of this paper is characterization of the quality of the interface between GdSiO and silicon. This quality is measured in terms of channel mobility extracted from split CV measurements and changes of charge trapped in the oxide and interface trap density under constant voltage stress. The latter effect is studied by means of a combination of C–V, I–V and charge pumping measurements. To the authors’ knowledge charge pumping measurements on devices with GdSiO dielectric are presented for the first time.
Section snippets
Experimental
nMOSFETs with GdSiO gate dielectric have been fabricated on (1 0 0) bulk silicon (substrate resistivity of 15–25 Ω cm) using a gate first integration approach. For GdSiO, a 4 nm thermal oxide interlayer has first been grown followed by 10 nm Gd2O3 deposited by e-beam evaporation [2]. For gate electrode, a mid-gap TiN metal inserted polysilicon stack (MIPS) has been used. Dopants for source and drain have been activated at 930 °C after self aligned ion implantation. This high temperature step has also
Summary
nMOSFETs with GdSiO gate dielectric were characterized by means of split C–V, I–V and charge pumping measurements. The obtained peak mobility was ∼120 cm2/V s and a rather high series resistance of ∼28 kΩ was extracted. The influence of frequency on CP measurements and that of voltage stress on CP, C–V and I–V (including gate current) measurements were studied. The extracted density of interface traps increased with decreasing frequency indicating the presence of border traps. It was found that
Acknowledgements
This work has been supported by Polish Ministry of Science and Higher Education under research Project No. 515444933 and by the European Community’s 7th Framework Programme (FP7/2007-2013) under Grant agreement n°216171 – NANOSIL. The authors express their gratitude to Prof. Olof Engström from Chalmers University of Technology for helpful discussion.
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