Elsevier

Microelectronics Reliability

Volume 81, February 2018, Pages 274-286
Microelectronics Reliability

Towards AND/XOR balanced synthesis: Logic circuits rewriting with XOR

https://doi.org/10.1016/j.microrel.2017.12.031Get rights and content

Highlights

  • XOR-And-Inverter Graph (XAIG) introduced

  • Rewriting algorithm based on XAIGs introduced and compared with standard AIG-based rewriting

  • Different XOR node costs are assumed and compared.

  • The results show that using XORs in logic synthesis in a balanced way is essential for obtaining good results.

Abstract

Although contemporary logic synthesis performs well on random logic, it may produce subpar results in XOR-intensive circuits. This indicated the need of equal status of XORs and ANDs, with their respective Negation-Permutation-Negation (NPN) equivalents in logic synthesis procedures. To test the hypothesis of XOR importance, we introduced a novel logic representation with a native support of XOR gates, the XOR-AND-Inverter Graph (XAIG). As the first test, we implemented a rewriting algorithm in the logic synthesis and optimization package ABC and compared it with the standard rewriting algorithm based on the AND-Inverter Graph (AIG). The main experimental evaluation was performed in the context of a complete logic synthesis process, particularly the FPGA LUT mapping and mapping to standard cells. To eliminate algorithmic noise, input circuit descriptions were randomly modified while preserving their semantics. In the FPGA mapping, the XAIG rewriting dominated the AIG procedure in 8.6% of cases, while it was dominated in 1.6% of cases. For the standard cells mapping, the respective percentages were 3% and 1.5%. We conclude that the best rewriting is a combination of both approaches.

Introduction

Logic synthesis is seen as a mature process, accepted by the electronic industry. Yet there appeared example circuits, which lead to provably unacceptable results [1], [2]. Although we proved that the loss of the original, designer-conceived structure played a significant role [3], other aspects were found contributing. One of those aspects was the treatment and employment of XOR operators during synthesis. We found that to introduce XORs at the technology mapping phase is too late. If the result of logic synthesis is too large (as a consequence of neglecting XORs), technology mapping does not have enough power to rearrange the circuit. As current activities [4] show, the role and importance of XORs in logic synthesis algorithms is still an open topic.

Scalability is a primary requirement for logic synthesis. Contemporary procedures achieve scalability by iterative transformations of regions of the circuit. Such an approach is called resynthesis. It must assume that even the original circuit description has already some relevant structure. The number of iterations is limited by available computing time and by the ability of the procedure to maintain convergence. Layered heuristics therefore help the procedure to converge to an acceptable result within acceptable computing time.

For combinational synthesis to be scalable, the size of the region selected for a transformation must not strongly depend on the circuit size, and the region must be small enough for the intended transformation. Optimum implementations can be stored for such small regions [5], or they can be computed using exact synthesis [6], [7], [8], [9].

Various types of regions have been defined to suit particular transformations. Windows are defined in terms of transitive fan-in and fan-out of a selected node. They form the base of the resubstitution algorithm [10]. Regions called cuts come from FPGA technology mapping, originally intended to represent the logic implemented by a Look-Up Table (LUT) [11], [12], [13]. They started to be widely used for other purposes after efficient cut enumeration procedures had been designed [5], [12], [14]. The rewriting algorithm in ABC [5] is a combination of cut enumeration with stored optimum implementations of the cut function.

The circuit representation underlying these and similar algorithms is in most cases a restricted version of a Boolean network. The restriction lies in the allowed repertory of node functions and in the fan-in of each node. For example, NAND networks used in classical library-based technology mapping [15] permit only one node function with the fan-in of two.

While Boolean networks are important for building the structure of a circuit and for selecting transformed regions, a high-performance representation of Boolean functions (without regard of the implementing structure) is sometimes required. For this purpose, Binary Decision Diagrams (BDDs) [16], [17] are widely used. The structure of the circuit is then built using another representation [18], [19], [20], [21].

In Boolean networks with a single node function only (homogeneous networks), many operations, such as comparison, are of purely structural nature. Instead of Boolean reasoning, graph algorithms are used. Also, a degree of canonicity can be achieved by structural means, that is, if a node intended for insertion into the network has the same predecessors as another node, that node can be used instead. In the paper [22], this technique is called structural hashing.

There is a price to these advantages. The limited repertory of node functions prevent some logic operators from being represented directly. They must be replaced by a sub-circuit built from permitted nodes. This may or may not correspond to reality: the actual cost of the replaced operator may be less than the total cost of the replacing nodes. An algorithm operating on such a representation is biased towards operators that can be represented directly.

Circuit representation in purely homogeneous networks tended to be large with too many equivalent representations of a single circuit. Better expressivity was achieved by introducing two edge types, namely, inverting and non-inverting edges. All contemporary network types use this feature.

The most widespread network of this kind is And-Inverter Graph (AIG) [5], [23], [24], [25]. The ABC system is a well-known implementation of numerous AIG-based algorithms [26]. In AIGs, an AND node with fan-in of two can, in combination with negation on adjacent edges, express any member of the NPN class comprising the AND operator [24], [27]. The other NPN classes of two-input functions (XOR derivatives) can be represented only indirectly as subgraphs.

Another homogeneous network is Majority-Inverter Graph (MIG) [6], [28], with majority of three variables as the node function. As AND is a specialization of majority (with one input at 0), MIG can be viewed as a generalization of AIG. Yet, majority is monotonic, which forces non-monotonic functions, such as XOR, to be represented indirectly again.

The bias introduced by homogeneous networks probably caused the shift of focus towards heterogeneous networks, even at the cost of more complex algorithms. MIGs were augmented to form XOR-Majority Graphs (XMG) [4]. In the ABC system, a facility implementing Boolean networks with AND, XOR and MUX nodes together with negated edges, was established.

We can see that the circuit representation can affect synthesis algorithms. The bias towards directly represented elements has been already discussed. Another influence comes from the limited number of iterations explained above. What is a single transformation of a heterogeneous network, can require multiple steps in other networks. Hence, with some representations, the procedure can converge slower or does not find a given solution at all.

Resynthesis algorithms can be formulated on many representations, both homogeneous such as MIG [29] or heterogeneous such as XMG [4]. The difference from the original (e.g., AIG) formulation is that some operations which were structural in homogeneous networks become functional (Boolean) [30]. There are already functional operations in homogeneous networks. For example, functional hashing reuses a node already providing the required Boolean function of primary inputs rather than constructs a new node. Despite its origin in AIGs, functional hashing can be obviously used with any Boolean network.

In the above described networks, XORs are rarely represented directly, which could suggest certain algorithmic bias against them. To judge the role of XORs, we need a representation where ANDs and XORs would be equally ‘first class citizens’, with balanced roles. The structure must be simple enough to permit adaptation of most base ABC algorithms, and as close as possible to AIGs for fair comparison (which unfortunately, excludes XMGs). Also, the difficulties caused by making the network heterogeneous should be kept small.

We presented such structure, called XOR-AND-Inverter Graphs (XAIGs) in [31], [32]. We based its experimental implementation on existing heterogeneous network in ABC, that is, on the GIA Manager facility [30].

To obtain first partial answers to the question of XOR importance, we modified one of ABC algorithms to use XAIGs. We have chosen rewriting, because the algorithm [5] is based on functional rather than structural matching, and hence allows easy generalizations. We evaluated XAIG rewriting against AIG rewriting experimentally, while screening the experiments from algorithmic noise. We found that XAIGs can indeed bring better results, but that the best approach is to combine both procedures.

Let us note that the evaluation of XOR importance was the leading motive rather than achieving superior results. Furthermore, the modification of the rewriting algorithm is a pilot experiment to show whether other algorithms shall also be adapted.

Even though both XMGs and ABC GIA AND-XOR-MUX-Inverter graphs are generalizations of XAIGs, they are not suitable for our purposes; the question we seek an answer for, is whether treating XORs and ANDs in a balanced way will improve the performance of logic synthesis. Therefore, the set of operators must be restricted to AND and XOR nodes only. Next, MIGs (and thus also XMGs) could be inefficient for “conventional” technology mapping [33], which could disturb the experimental comparison.

This paper is a continuation of the work proposed in [31] with more relevant evaluation experiments and extended discussion. The paper is organized as follows: after the Introduction and some preliminaries in Section 2, the proposed XAIG structure is described in Section 3, with implementation issues presented in Section 5. The newly introduced rewriting algorithm based on the XAIG structure is presented in Section 4. Section 6 contains experimental results. Section 7 discusses the benefits and difficulties of the XAIG approach and Section 8 concludes the paper.

Section snippets

And-Inverter Graphs

And-Inverter Graphs (AIGs) [5], [23], [24], are directed acyclic graphs with one or more roots, where nodes are two-input AND gates and edges represent connections between them. Edges may be inverted, meaning that the respective subgraph is negated. This can be understood as an inverter presence on the connection.

In such a formalism, even simple Boolean functions can have many representations. To achieve some degree of canonicity, the ABC system enforces several rules for AIGs.

AIGs are

The XAIG structure and its properties

XAIG is a directed acyclic graph, where nodes are two-input ANDs or XORs, while edges can be inverted. As seen in Fig. 3, XOR is described by 3 AND nodes in AIG, which can make it more difficult for algorithms to utilize it. In XAIGs, XOR is represented as a single node.

XAIGs are a generalized form of AIGs; every AIG can be considered as an XAIG with no XOR nodes. Therefore, XAIG (just like AIG) can implement any logic function.

The AIG techniques for partial canonicity (structural hashing)

XAIG-based rewriting algorithm

In order to make logic synthesis and optimization work more efficiently with XOR gates, probably all algorithms employed should be modified accordingly. As the first step towards the balanced synthesis [36] and to demonstrate whether synthesis actually needs to be capable of a native work with XOR gates, we introduced an XAIG rewriting algorithm based on AIG rewriting presented in Ref. [5].

Rewriting is a technique of replacing AIG (XAIG, in our case) subgraphs with K leaves (K-feasible cut

The ABC GIA manager

The ABC9 package features a new manager for AIG manipulation, the GIA manager, as an alternative to the standard AIG manager [30]. The purpose of this manager is mostly experimental. Compared to the AIG manager, it is more memory-efficient and provides a faster way to search for certain structural patterns, therefore it is used mostly for the purpose of conversion between different logic representations. On the other hand, it is less effective in performing AIG modifications.

The GIA manager

Experimental results

As a comparison of the AIG-based synthesis performance with the XAIG-based synthesis, we have run both rewriting algorithms over a set of more than 700 benchmark circuits obtained as a mix of different benchmarks: LGSynth‘91 [41], IWLS‘93 [42], ISCAS‘85 [43], ISCAS‘89 [44], ITC‘99 [45], LEKO/LEKU benchmarks [1], EPFL [46] and IWLS 2005 [47] — available from Ref. [48].

Compared procedures and replacements

To answer the question of XOR importance experimentally, two procedures should be compared, one with XORs and one without, but identical otherwise. This represents the comparison A in Fig. 13. There are other factors, however, which affect the comparison.

The first one is the number of replacements. In Ref. [31], we used a single replacement for each NPN class, yielding the comparison B in Fig. 13. The results were negatively affected, so that the comparison could not be fair. The experiment in

Conclusion

A novel circuit representation structure – the XOR-AND-Inverter Graph (XAIG) – was proposed in this article, together with a rewriting algorithm based on this representation. The algorithm was implemented in the framework of logic synthesis and optimization tool ABC. The XAIG-based rewriting algorithm was compared to the original AIG-based rewriting already implemented in ABC. The results indicate that the new algorithm is stronger in XOR identification and in reducing the number of nodes than

Acknowledgment

This research has been partially supported by the grant GA16-05179S of the Czech Grant Agency, “Fault-Tolerant and Attack-Resistant Architectures Based on Programmable Devices: Research of Interplay and Common Features” (2016–2018) and by the grant SGS17/213/OHK3/3T/18.

Computational resources were provided by the CESNET LM2015042 and the CERIT Scientific Cloud LM2015085, provided under the programme “Projects of Large Research, Development, and Innovations Infrastructures”.

Last, but not the

Ivo Háleček received his MSc. degree in Computer Engineering at the Czech Technical University in Prague in 2015. He currently studies Ph.D. at the same university, Faculty of Information Technology. His main area of interest is logic synthesis.

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  • Ivo Háleček received his MSc. degree in Computer Engineering at the Czech Technical University in Prague in 2015. He currently studies Ph.D. at the same university, Faculty of Information Technology. His main area of interest is logic synthesis.

    Petr Fiser received his MSc. and Ph.D. degrees in Computer Science and Engineering at the Czech Technical University in Prague in 2002 and 2007, respectively. He currently works as an associate professor at the same university, Faculty of Information Technology. His main areas of interest are logic synthesis, two-level and multi-level optimization, build-in self-test (BIST), test generation, compression and on-line testing.

    Jan Schmidt received his MSc. and Ph.D. degrees in Computer Science and Engineering at the Czech Technical University in Prague in 1976 and 2001, respectively. He currently works as an associate professor at the same university, Faculty of Information Technology. His main areas of interest are logic synthesis, two-level and multi-level optimization, finite-field arithmetics, and EDA.

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